Unit 1 - Components of a Comptuer Flashcards

You may prefer our related Brainscape-certified flashcards:
1
Q

What is the role of the Control Unit? (3)

A
  • Coordinates the processor.
  • Directs the flow of data between the CPU and other components
  • Decodes instructions into operand and opcode.
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
2
Q

What is the role of the ALU?

A
  • Performs arithmetic, logical, and shift operations.
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
3
Q

What are registers?

A
  • Superfast and small memory locations to temporarily store data.
  • Onboard the CPU
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
4
Q

What are buses?

A
  • A series of parallel wires connecting the internal components of a computer.
  • Usually 8, 16, 32, or 64 lines where each line carries 1 bit.
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
5
Q

What is the role of each register?

A
  • Program Counter (PC): holds memory address of next instruction to be executed. Incremented by one each cycle.
  • Memory Address Register (MAR): holds the address in memory
  • Memory Data Register (MDR): temporarily holds the data
  • Current Instruction Register (CIR): holds the current instruction - divided up into operand & opcode
  • Accumulator: stores results of the calculations performed in the ALU
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
6
Q

How are the three buses used?

A
  1. Address of memory location which CPU is trying to access is sent on the Address Bus.
  2. This data is sent to the CPU on the Data Bus.
  3. Control signals between internal and external comps. are sent along the Control Bus.
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
7
Q

What does the control bus do and what are the control signals?

A

Transmits control signals, coordinates use of other 2 buses, and provides status information between components.

Bus Request: Shows a device is requesting use of a data bus.
Bus Grant: Shows CPU has granted access to data bus.
Memory Write: Data’s written into addressed location.
Memory Read: Data read from a location to be placed on data bus.
Interrupt Request: Shows a device is requesting access to CPU.
Clock: used to synchronise operations

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
8
Q

Name 1 Optical, 1 Magnetic and 1 Flash storage devices and its key features/characteristics.

A

Optical: CD’s - Limited capacity, very portable, easily damaged.

Magnetic: - Hard Disk Drives - High capacity, slow data transfer speeds.

Flash: Solid State Drives - Fast, Compact/Light, Portable, Durable(no moving parts), Expensive, Short Life Span.

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
9
Q

What are the differences between Complex Instruction Set Computing (CISC) and Reduced Instruction Set Computing (RISC)? (learn 4/8 at least)

A

Usage: CISC is used in laptops and desktop computers, RISC is used in smartphones and embedded systems

Hardware: CISC has more complex hardware, RISC has simpler hardware

Software: CISC supports for simpler software development, RISC software development is more complex

FDE cycles: CISC uses multiple FDE cycles per instruction meaning less RAM is needed to store instructions, RISC uses a single FDE cycle per instruction meaning more RAM needed

Size: CISC is physically larger and requires more silicon, RISC is smaller and requires less silicon

Energy consumption: CISC consumes more energy, RISC consumes less energy (longer battery life) and can go into sleep mode

Pipelining: CISC uses varied instruction lengths so it cannot support pipelining, RISC uses standardised instruction lengths to allow pipelining

Cost: CISC is more expensive due to its complex hardware and larger size, RISC is cheaper because of its simpler hardware and smaller size

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
10
Q

What is the difference between parallel/concurrent processing and pipelining?

A
  • Pipelining utilised CPU registers and the ALU when they are idle by fetching an instruction while one is being decoded and another is being executed.
  • Parallel/concurrent processing utilises CPU cores by performing FDE cycles in each core simultaneously.
How well did you know this?
1
Not at all
2
3
4
5
Perfectly
11
Q

What are the differences between Von Neumann and Harvard architecture?

A

Von Neumann architecture:
- Instructions and data are stored in the same memory and transferred using a single shared bus
- Instructions and data have to be transferred through the same bus which bottlenecks performance
- Instructions and data need to have the same word length because they share the same bus
- Used in PCs, laptops, etc.

Harvard architecture:
- Instructions and data are stored separately and are transferred using their own busses
- Instructions and data do not have to compete for the same bus
- Instructions and data can be different sized word lengths
- Used in embedded systems and cache memory

How well did you know this?
1
Not at all
2
3
4
5
Perfectly