Topic 11 theory Flashcards
CPU Instruction cycle and activities
Fetch instructions, decode instructions, fetch data, process data, write data.
4 Instruction cycles
Fetch,execute,interrupt,indirect
Indirect instruction cycle
check for any indirect addressing involved, if so required operands are fetched using indirect addressing
Decoding of indirect addressing is done by?
Control unit
Branch penalty
Conditional branch makes next instruction address unknown.
If a branch is taken, pre-fetched instruciton must be discarded to fetch new instructions.
unable to achieve execution time = fetch time
Six stage Instruction pipeline instructions
- Fetch Instruction
- Decode Instruction
- Calculate Operands
- Fetch Operands
- Execution Instruction
- Write Operand
Issues of instruction pipeline
Branch penalty, Interrupt invalidating pre-fetched instructions, Somse stages depending on the contents of register, can be altered by previous instructions still in pipeline.
Potential issues of multi stage pipeline
Overhead in moving data and functions, lengthens execution time.
amount of control logic required to optimize increases enormously
Total time of non pipeline
n = instructions,
k = stages
clock cycle time
n x k x clock cycle time
total time of pipelined
n = instructions
k = stages
(k+ (n - 1) ) x clock cycle time
speed up factor
total non pipeline time / total pipeline timer
Pipeline hazards
when pipeline stalls as condition do not permit execution
Resource/structural hazards
When two or more instructions in the pipeline uses the same resources, instructions are executed in series rather than parallel
Data hazard
Conflict in accessing an operand location, two instructions are executed in sequence
Control hazard
make wrong decisions on branch predictions
