Thread-Level Parallelism Flashcards

1
Q

What is Uniform Memory Access?

A

UMA is a shared memory multiprocessor architecture type where each processor takes the same amount of time to access any memory location. The processors are connected by a bus or on-chip/on-board interconnect

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2
Q

What is Non-Uniform Memory Access?

A

NUMA is a shared memory multiprocessor architecture type where memory access times are not similar across processors. It depends on the processor’s proximity to the memory

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3
Q

What is the “Shared” state in the MESI protocol?

A

The cache line is clean (not modified) and there may be multiple copies

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4
Q

What is the “Exclusive” state in the MESI protocol?

A

The cache line is clean (not modified) and only a local copy exists

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5
Q

What is the “Modified” state in the MESI protocol?

A

The cache line is dirty (modified) and only a local copy exists

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6
Q

What is the “Invalid” state in the MESI protocol?

A

The local copy of the cache line is invalid

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7
Q

If the memory state is “Shared” and there is a local write to it, what must be done?

A
  1. Update state to “Modified”
  2. Issue bus upgrade
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8
Q

If the memory state is “Exclusive” and there is a read detected on the bus to it, what must be done?

A
  1. Respond “shared” on the bus line
  2. Update state to “Shared”
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9
Q

If the memory state is “Modified” and there is a read detected on the bus to it, what must be done?

A
  1. Respond “dirty”
  2. Write data back
  3. Update state to “Shared”
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10
Q

What does the “upgrade” bus transaction do?

A

Upon modifying a block, “upgrade” invalidates the local copy of other processors if the block is shared

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11
Q

List the advantage and disadvantage of the “Owned” state in the MOESI protocol

A

Advantage: Reduces (slow) writebacks to memory
Disadvantage: Onus is on the owner

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12
Q
  1. In the MOESI protocol, when do write-backs to memory happen?
  2. What happens on a read-miss for a dirty block?
A
  1. Write-backs to memory occur just before block eviction
  2. The cache with the dirty block (aka the Owner) forwards it to the cache that triggered the read miss. The latter becomes the owner
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13
Q

What responsibility does the owner have in a MOESI protocol?

A

It must respond to all misses by other caches.

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14
Q

What is the forwarding state in the MESIF protocol?

A

The most recent reader of a clean block holds it in the forwarding state. It forwards the block on a miss request. Upon forwarding the block, it transitions to the shared state

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15
Q

What is a sharing vector in the directory cache coherence protocol? What are its fields?

A

A table/vector in each memory segment that tracks the blocks in each of the caches in its system. It stores the block number, a bit for where it is dirty, and a bit for each of the nodes to identify which node is reading from it.

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16
Q

What is the disadvantage of using a sharing vector to keep track of memory block usage?

A

Large overhead ~100%

17
Q

List 2 main synchronization mechanisms for two threads modifying the same memory

A
  1. Atomic primitives
  2. Guard critical sections with locks (1 = locked, 0 = open)
18
Q

How are load reserves broken?

A

When other processors write to the same block

19
Q

What is a store conditional instruction?

A

Stores data in memory if the reservation is still held by the processor

20
Q

What is the lfence instruction?

A

An x86 instruction that finishes all prior loads before the next instruction is executed

21
Q

What is the sfence instruction?

A

An x86 instruction that finishes all prior stores before the next instruction is executed

22
Q

What is the mfence instruction?

A

An x86 instruction that finishes all prior loads and stores before the next instruction is executed

23
Q

How is Total Store Ordering (TSO) different from sequential consistency?

A

TSO relaxes the W->R ordering whereas sequential consistency maintains all 4