Out of Order Pipelines (Memory)

Question 1

What are the 4 sections of program data? What is stored in each of them

Answer 1

i. text (program literals)
ii. data (global variables)
iii. heap (dynamically allocated memory and large structures)
iv. stack (local variables AND spilled registers)

Question 2

What is an address generation unit (AGU)?

Answer 2

It is a dedicated functional unit that is used to compute the effective address (EA) before performing loads/stores

Question 3

How do you speed up the calculation of effective addresses in out of order pipelines?

Answer 3

Using an address generation unit (AGU)

Question 4

How are stores carried out in out-of-order pipelines?

Answer 4

1. Calculate EA
2. Put EA + data in store buffer
3. After commit, retire to D-cache when D-cache is idle

Question 5

How are loads carried out in out-of-order pipelines?

Answer 5

1. Calculate EA
2. Read data from D-cache or SB
3. Broadcast data on forwarding bus

Question 6

How are exceptions handled in memory operations of out of order pipelines?

Answer 6

When a faulting instruction reaches the head of the ROB, any finished stores are flushed and any committed stores are permitted to retire

Question 7

What is the difference between a finish and a commit in out-of-order execution?

Answer 7

In a finish, the data is simply broadcast on the forwarding bus. On a commit, it is saved to the destination register.

Question 8

What are the steps for speculative loading?

Answer 8

1. Calculate EA
2. Use data from most recent aliased store (otherwise get data from d-cache)
3. Add to finished load buffer (FLB)
4. On commit, remove from FLB

Question 9

What are the steps for speculative storing?

Answer 9

1. Calculate EA
2. Put EA + data in SB
3. On commit, if aliased load is present in FLB, squash it
4. Retire to D-cache when idle

Question 10

What does the “tag” in the FLB represent?

Answer 10

The PRF (physical register file) number

Question 11

What is the disadvantage of speculative loads?

Answer 11

Valid loads may be squashed

Edit: Invalid speculative loads must be restarted

Question 12

What is the disadvantage of using software prefetching?

Answer 12

The compiler needs to know where to insert them in code

Question 13

What is streaming (with reference to prefetchers)?

Answer 13

Loading consecutive blocks

Question 14

What is striding (with reference to prefetchers)?

Answer 14

Loads with regular stride (e.g. reading a column of array stored in row-major order)

Question 15

What is a problem with prefetching into the cache? How is it solved?

Answer 15

Erroneous prefetch “pollutes” cache with unneeded data, reducing hit rate. Can be solved by prefetching into a prefetch buffer, loading into cache only if demanded by the program

Question 16

What are the steps for Age-Based Loading?

Answer 16

1) Calculate EA
2) Check SB for aliases between head and tail pointers and use data (Otherwise if miss, read from D-cache)
3) Broadcast on forwarding bus

Question 17

What are the steps for Age-Based storing?

Answer 17

-> Same as OOO store!
1) Calculate EA
2) Put EA + Data into SB
3) After commit retire to D-cache when idle

Question 18

What are the contents of the MRP (Memory Reference Predictor)?

Answer 18

Load instruction address, effective address (EA)/data address, stride

Question 19

How is the stride calculated in order to populate the MRP?

Answer 19

if instruction address already present, stride = newEA - oldEA
if instruction address is new, 1 (or 4 or 8), depending on the requested data size

Question 20

How is the MRP used by the Instruction Fetch Unit (IFU)?

Answer 20

The IFU checks the PC in MRP. If there is a hit, it means the instruction being fetched is a previously executed load. Add the stride to the last EA and perform a touch on the cache. The touch operation initiates a memory transfer

Question 21

What unit interacts with the MRP?

Answer 21

Instruction Fetch Unit (IFU)