The Processor Flashcards

1
Q

Purpose of the CPU

A
  • To process machine instructions
  • Carry out the fetch-decode-execute cycle
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2
Q

3 Main components of CPU

A

CU, ALU, RAM

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3
Q

What is the CU?

A

Control Unit: Sends control signals to other components - responsible for organising the FDE of instructions - controls input/output devices - communicates with all parts of the CPU

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4
Q

What is the ALU?

A

Performs calculations and makes logical decisions

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5
Q

What is RAM?

A

Holds the data and instructions for the currently running programs

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6
Q

What are registers?

A

Stores the programs which are needed instantly e.g. software applications

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7
Q

5 registers

A

1) Accumulator
2) PC
3) CIR
4) MDR
5) MAR

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8
Q

Accumulator

A

Holds the data currently being processed - results of calculations carried out by ALU

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9
Q

Program Counter

A

Holds the memory address of the next instruction to be executed - increments the next instruction to be fetched

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10
Q

Current Instruction Register

A

Stores the address of the instruction currently being executed

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11
Q

Memory Data Register

A

Stores data being transferred temporarily - all data to and from memory must travel down the data bus and pass through the MDR

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12
Q

Memory Address Register

A

Stores the address of the memory location currently in use - sends address to memory down the address bus

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13
Q

Address Bus

A

Carries the address of the memory locations

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14
Q

Data Bus

A

The contents of the instruction are carried

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15
Q

Control Bus

A

Informs whether the info is read or write control signals

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16
Q

Bus Width

A

The number of wires that make up a bus - determines the range of instructions that can be transmitted

17
Q

Fetch Stage

A
  • PC register displays the address in RAM of the next instruction to be processed
  • This value is copied into the MAR
  • The PC is incremented by 1
  • This prepares the CPU for the next instruction to be fetched
  • The CPU checks the address in RAM which matches the address held in the MAR
  • The instruction in RAM is transferred to the MDR
  • The instruction in the MDR is copied into the CIR
18
Q

Decode Stage

A

The instruction in the CIR is understood and decoded - CU sends signals using the 3 busses

19
Q

Execute Stage

A

Any result of an execution is stored in the ACC register

20
Q

Clock Speed

A

How many CPU cycles can be run per second - the bigger the number the more cycles can be run per second

21
Q

Overclocking

A

Making a computer or component operate faster than the clock frequency specified by the manufacturer - system can become unstable and there is a risk of damage due to excessive heat generation

22
Q

Cache

A

Cache memory is used as the RAM is significantly slower than the speed CPUs operate - fast memory built into the processor reducing the distance data has to travel to it

23
Q

Cores

A

Additional processors

24
Q

Increasing the number of cores

A

Ensures cycles can be run simultaneously

25
Increasing cache size
Ensures more frequently used programs can be accessed much faster
26
Multicore Processor
Single chip containing two or more independent processing units - each core can FDE its own instructions
27
Chip with 2 cores
Dual-core processor
28
Chip with 4 cores
Quad-core processor
29
Limitation of multicore processing
Double the number of cores does not mean double the performance (overheads involved with inter-core communication, some programs cannot make maximum use of all cores
30
Parallel Processing
The processing of program instructions by dividing them between multiple processors or processor cores
31
Limitation of parallel processing
The extent parallel processing can speed up computation depends on the task being carried out and if the software is designed to make use of parallel processing
32
Co-processor
Any additional processor used for a specialised task - improves the overall speed of a computer by executing concurrently
33
Graphical Processing Unit (GPU)
- Run slower than a CPU core - Highly specialised - superior in speed and efficiency for certain tasks - Better than CPUs for larger data sets