The characteristics of contemporary processors, input, output and storage devices Flashcards
What is the Control unit? What are some of its roles?
Component of processor which directs operations of the CPU
-Decoding instructions
-Accepting next instruction
-Manages flow of data between CPU and other devices
-Stores resulting data back in memory
Coordinating activities of CPU
What is meant by the term ‘buses’?
They are a set of parallel wires which connect two or more components inside the CPU
Name the buses in the CPU
-Data bus
-Address bus
-Control bus
What is meant by the ‘bus width’?
The number of parallel wires a bus has
-Buses are typically 8,16,32 or 64 wires wide
The bus width is directly proportional to…
the number of bits that can be transfered simultaneously at any given time
(so bus width of 8 bits means 8 parallel buses as only one bit can be transfered per bus at a time)
Data bus
Its a bidirectional bus used for transporting data and instructions between components
What is meant by a ‘bidirectional bus’?
Bits can be carried in both directions
Address bus
This bus is used to transmit the memory addresses which specify where data is to be sent to or retrieved from
The width of an address bus is..
directly proportional to the number of addressable memory locations
(as more bits can represent more memory address combinations)
Which buses are bidirectional and which ones are unidirectional?
Bidirectional = Data bus, Control bus
Unidirectional = Address bus
Control bus
This is a bidirectional bus
-Used to transmit control signals between internal and external components
-Coordinates the use of the data and address buses
-Provides status info between system components
Give examples of control signals
Transmitted using control bus
-Memory read
-Memory write
-Bus grant
-Bus request
-Clock signal (used to synchronise operations)
-Interrupt request (shows device is requesting access to CPU)
What is meant by a memory read and write control signal?
-Memory read
The CPU uses the address bus to specify the memory location (address) from which data is to be read.
The control bus sends a signal (e.g., READ) to indicate that a memory read operation is taking place.
The data at the specified memory location is placed on the data bus and transferred to the CPU.
-Memory write
The CPU uses the address bus to specify the memory location (address) where the data will be written.
The control bus sends a signal (e.g., WRITE) to indicate that a memory write operation is occurring.
The data to be written is placed on the data bus and transferred to the specified memory location.
What is meant by a bus grant and a bus request control signal?
Bus request = Device is requesting use of a bus
Bus grant = CPU has granted access to a bus to a device
Assembly language
Uses mnemonics to represent instructions
-Simplified way of representing machine code
-Instruction is divided in the CIR into opcode and operand
What is the difference between opcode and operand?
Opcode= The type of instruction to be executed (eg ADD)
Operand= Data or address of the data which the operation is to be carried on
Some bits in the operand are addressing modes
What is pipelining?
Two types: Instruction and arithmetic pipelining
-The process of completing the FDE cycles of 3 separate instructions simultaneouly
-Aimed at reducing the amount of the CPU which is kept idle.
—Holding some data in a buffer close to the CPU until its required
—While one instruction is being executed another can be decoded and another can be fetched
What is the difference between arithmetic and instruction pipelining?
Instruction=Improves the execution of instructions carried out by CPU: Separating instruction into fetching, decoding and executing and overlapping these stages for each instruction
Arithmetic= Used in arithmetic operations: Breaking down the arithmetic operations and overlapping them as they are performed for each instruction
What does pipelining aim to do?
Aimed at reducing the amount of CPU which is kept idle (unused/inactive)
What is meant by the FDE cycle?
Sequence of operations that are completed in order to execute an instruction
What happens in the Fetch stage of the FDE cycle?
- Program Counter holds the memory address of the next instruction to be fetched which is transferred to the Memory Address Register (MAR) via the address bus, which is used to specify the location in memory to fetch the instruction from. The address bus passes this into memory
- The Control Bus sends a signal to memory, instructing it to read the value at the address specified in the MAR.
The instruction stored at that memory address is fetched from main memory (RAM). - Data bus carries the instruction from the memory location to the Memory Buffer Register (MBR)
- After the instruction is fetched, the Program Counter (PC) is incremented to point to the next instruction. This ensures that the next cycle fetches the correct instruction from the next memory address.
What happens in the Decode stage of the FDE cycle?
- The instruction fetched from memory in the Fetch stage is now stored in the current Instruction Register
- The instruction is split up into two parts:
Opcode: The operation to be performed (e.g., ADD, SUB).
Operand: The data or memory address the operation will act upon (e.g., a number or a memory location). - Control Unit decodes the opcode part of the instruction. The opcode tells the Control Unit what operation is needed
Based on the opcode, the Control Unit generates the appropriate control signals to carry out the operation. For example: - Control Unit prepares the Arithmetic Logic Unit (ALU) or other functional units for the operation defined by the opcode.
What happens in the Execute stage of the FDE cycle?
Decoded instruction is executed
This can be: (if its a calculation)
Control Unit sends control signals to the relevant parts of the CPU to carry out the operation defined by the opcode (instruction type).
Control Unit ensures that the correct ALU operation is triggered, or that the correct memory or register operation is performed.
Give me factors affecting CPU performance
-Clock speed
-Number of cores
-Cache (amount and type of cache memory)
-Address bus width
-Data bus width