The characteristics of contemporary processors, input, output and storage devices Flashcards
What is the Control unit? What are some of its roles?
Component of processor which directs operations of the CPU
-Decoding instructions
-Accepting next instruction
-Manages flow of data between CPU and other devices
-Stores resulting data back in memory
Coordinating activities of CPU
What is meant by the term ‘buses’?
They are a set of parallel wires which connect two or more components inside the CPU
Name the buses in the CPU
-Data bus
-Address bus
-Control bus
What is meant by the ‘bus width’?
The number of parallel wires a bus has
-Buses are typically 8,16,32 or 64 wires wide
The bus width is directly proportional to…
the number of bits that can be transfered simultaneously at any given time
Data bus
Its a bidirectional bus used for transporting data and instructions between components
What is meant by a ‘bidirectional bus’?
Bits can be carried in both directions
Address bus
This bus is used to transmit the memory addresses which specify where data is to be sent to or retrieved from
The width of an address bus is..
directly proportional to the number of addressable memory locations
Which buses are bidirectional and which ones are unidirectional?
Bidirectional = Data bus, Control bus
Unidirectional = Address bus
Control bus
This is a bidirectional bus
-Used to transmit control signals between internal and external components
-Coordinates the use of the data and address buses
-Provides status info between system components
Give examples of control signals
Transmitted using control bus
-Memory read
-Memory write
-Bus grant
-Bus request
-Clock signal (used to synchronise operations)
-Interrupt request (shows device is requesting access to CPU)
What is meant by a memory read and write control signal?
-Memory read (the data is read from a specific location to then be placed onto the data bus)
-Memory write (the data is then written into the addressed location using the control bus)
What is meant by a bus grant and a bus request control signal?
Bus request = Device is requesting use of data bus
Bus grant = CPU has granted access to the data bus to a device
Assembly language
Uses mnemonics to represent instructions
-Simplified way of representing machine code
-Instruction is divided in the CIR into opcode and operand
What is the difference between opcode and operand?
Opcode= The type of instruction to be executed (eg ADD)
Operand= Data or address of the data which the operation is to be carried on
Some bits in the operand are addressing modes
What is pipelining?
Separated into: Instruction and arithmetic pipelining
-The process of completing the FDE cycles of 3 separate instructions simultaneouly
-Aimed at reducing the amount of the CPU which is kept idle.
—Holding some data in a buffer close to the CPU until its required
—While one instruction is being executed another can be decoded and another can be fetched
What is the difference between arithmetic and instruction pipelining?
Instruction= Separating instruction into fetching, decoding and executing
Arithmetic= Breaking down the arithmetic operations and overlapping them as they are performed
What does pipelining aim to do?
Aimed at reducing the amount of CPU which is kept idle
What is meant by the FDE cycle?
Sequence of operations that are completed in order to execute an instruction
X What happens in the Fetch stage of the FDE cycle?
Address from PC is copied to the MAR
Instruction held at that address is copied to the MDR by the data bus
Simultaneously the contents of the PC are increased by 1
Value held in the MDR is copied to the CIR
X What happens in the Decode stage of the FDE cycle?
Contents of the CIR are split into opcode and operand
X What happens in the Execute stage of the FDE cycle?
Decode instruction is executed
Give me factors affecting CPU performance
-Clock speed
-Number of cores
-Cache (amount and type of cache memory)
-Address bus width
-Data bus width
X Explain how the clock speed affects the perfomance of the CPU
Clock speed is determined by system clock
-System clock generates signals alternating between 0 and 1
X Explain how the number of cores affects the perfomance of the CPU
Explain how the cache affects the perfomance of the CPU
Cache is the CPU’S onboard memory
-Instructions fetched from main memory are copied to the cache so if they are need again the can be accessed quicker.
-Before looking in main memory first look inside the cache
-As the cache fills up unused instructions are replaced
What happens as cache fills up?
Unused instructions are replaced
Level 1 cache type
Very fast memory cells with small capacity
Level 2 cache type
Relatively fast memory cells with medium capacity
Level 3 cache type
Slower memory cells with large capacity
X Von Neumann architecture
Includes basic components of a computer and processor such as single CU, ALU, registers and memory units
SHARED memory and SHARED data bus is used for both data and instructions
Von Neumann architecture is built on the stored program concept
Von Neuman architecture is built on the…
stored program concept
X Harvard architecture
Physically seprate memories for instructions and data
Used more commonly in embedded processors
This is useful for when memories have different characteristics
Contemporary processing
What came first RISC OR CISC?
CISC processors where used as a standard at first but they got replaced with RISC with time
Know CISC are more used in embedded systems and microcontrollers
What does RISC stand for?
Reduced instruction Set Computers
What does CISC stand for?
Complex instruction Set Computers
RISC
REDUCED INSTRUCTION SET COMPUTERS
In these processors there is a SMALL instruction set
-Each instruction is approximately one line of machine code and takes one clock cycle
CISC
COMPLEX INSTRUCTION SET COMPUTERS
In these processors there is a LARGE instruction set, these instructions are built into the hardware
-Aim is to try and complete tasks in as few lines of assembly code as possible
X Comparison between RISC and CISC
RISC:Compiler has to do more work to translate HL code into MC
CISC: Compiler has less work to translate HL into MC
What is meant by a multi-core CPU?
They have multiple independent cores which can complete instructions separately ==> Results in better performance
What performs better and when multi-core systems or parallel systems?
Multicore perform better in larger projects
Describe the principles of Optical devices
These devices are read from and written to using a laser light
Laser shines on top of disc
Binary info is arranged in a spiral track. The laser starts reading from the inner edge and moves outward in a continuous spiral.
Pits scatter light they represent 0
Lands reflect light they represent 1
R: During reading, the laser shines on the disc, and the sensor detects the variations in light reflection caused by the pits and lands. The pattern of reflected and scattered light is interpreted as binary data.
W: When data is written, the laser alters the surface of the disc by creating pits and lands according to the encoded binary information.