Summary Review Flashcards
How would you send the error output from your program, a.out, to a file called error.txt?
./a.out 2> error.txt
Suppose you want to output an address in hex, what is the correct placeholder to use in your print statement?
%x
Which command allows you to write information to a specified output stream?
fprintf
Suppose you declare two variables:
int x;
int y;
Now you wish to read in two integers, separated by spaces, from stdin. What command would you use?
scanf(“%d%d”,&x,&y);
According to the text, a computer’s vocabulary is defined by its
instruction set
instruction set
if R3 = 0xffff_baad_c00f_0000, what value will be in R4 after this operation:
ASR R4, R3, #4
0xffff_fbaa_dc00_f000
0xffff_fbaa_dc00_f000
Mark all that are true of a RISC architecture
includes architectures, such as the x86 architecture.
tries to make common cases fast.
will use multiple instructions to carry out complex, less frequent operations.
.
In the ARM architecture, the MOV instruction sets a register to value. This value may come from (check all that apply):
a register
an immediate field
.
The ARM instruction SUB R3, R1, R2
performs R1 - R2 and puts the result in R3
.
The ARM instruction CMP
sets bits in the CPSR
sets bits in the CPSR
Given CMP R4, R2 which condition code bits would need to be set to indicate that R4== R2
Z
Given the following C code and its corresponding Assembler, select the appropriate instruction to put in the blank spot:
i = 10;
j = 1;
while (i > 0){
j = j + i;
i--;
}
mov R2, #10 ; i/R2 = 10
mov R3, #1 ; j/R3 = 1
lp: cmp R2, #0 ; while (i > 0){
\_\_\_\_\_ ; .
add R3, R3, R2 ; j/R3 = j/R3 + i/R2;
sub R2, R2, #1 ; i/R2 = i/R2 - 1;
b lp ; }
done:
Consider the following code fragments where target has the address 0x1018 and from has the address 0x1000. What is the immediate offset that will be encoded into the branch instruction at 0x1000?
0x1000 from: b target 0x1004 sub r10, r10, r2 0x1008 lsl r10, r10, #4 0x100c and r10, r2 0x1010 lsr r10, r10, #4 0x1014 or r0, r0, r0 0x1018 target: add r0, r0, #1 0x101c str r0, [r5, #0x100]
0x00_0004
Right. The immediate is the number of instructions between the target 0x1018 and the PC of the branch +8. 0x1008.
There are 4 instruction in between.
If the OP field (bits 27:26) of an instruction is 00, then the instruction type is:
a data processing instruction
a data processing instruction
A load or store instruction can specify a base address (from a register) and
a 12-bit unsigned immediate
What does push {r0} do to the stack pointer?
Decrements sp before storing r0 onto the stack.
Decrements sp before storing r0 onto the stack.
What does pop {r0} do to the stack pointer?Increments sp after loading from the stack into r0.
Increments sp after loading from the stack into r0.
Function Prologue and Epilogue
The prologue is the set up at the start of a function, push lr, fp and any preserved registers onto the stack. The epilogue: clean up at the end of a function, pop anything you pushed onto the stack in the prologue.
pop and push
Preserved registers
Preserved registers are maintained by the person creating the program, this is NOT automatic! Preserved registers are a convention that you as the programmer must follow. What is means it that a function can assume any preserved registers (r4-r11) it uses will contain the same values even after a call to another function.
This means that if you have a function f1 that calls another function f2, when f2 is finished and returns to f1, f1 assumes all registers r4-r11 contain the same values that were stored in those registers before the call to f2. Therefore it is the job of f2 to make sure that the values that were stored in r4-r11 when f2 was called are back in those registers before it returns to f1.
lr is stored in the stack at the start of a function so we don’t lose our caller’s address during any nested function calls. Any use of BL in our function will overwrite the lr register.
Also, note that lr is a synonym to r11 (a preserved register)
Suppose we’re going to use registers r0 through r5 in a function.
What should we do in the prologue in addition to pushing fp and lr onto the stack?
Push r4 and r5 onto the stack.
Which registers should func1 be preserving (pushing and popping)?
func1: ; some code
BX lr
main: ; some code
BL func1
; some code
fp, lr and any preserved registers func1 uses
- We have the following int array arr. Values prefixed with “0x” are in hex. Values with no prefix are in decimal.
int arr[] = [10, 20, 30, 40, 50];
The base address of arr is 0x80.
What is the value of *(arr + 2)?
What is the value of (arr + 2)?
What is the value of *(arr) + 2?
What is the value of *(arr + 2)?
30
What is the value of (arr + 2)?
0x88
What is the value of *(arr) + 2?
12
CMP R3, R0
BGE one
CMP R1, #0
BNE two
one:
ADD R2, R1, R3
SUB R2, R2, R0
two:
MOV R0, R2if( p >= m || n == 0) {
o = n + p - m;
}
struct mystery {
int h;
int w;
char * name;
};
struct mystery * t = malloc(sizeof(struct mystery));
/* Assume there is code to properly initialize the height, weight, and name fields of the struct pointed to by t */
char start = /* Fill this in */
Which of the following options would correctly place the first character of t’s name into the variable start? For example, if name was “stormfighter”, then start should be ‘s’. Select ALL that apply.
*(t->name)
t->name[0]
Types of Memory
Global variables - Data Segment
• Local Variables - Stack
• Dynamically allocated memory - Heap
.
int * IncrementPtr (int *p) {
p = p +1;
return (p+1)
}
int A[3] = {50, 60 , 70};
int * q = A;
q = IncrementPtr(q);
what happens when IncrementPtr(q) is called?
‘q’ points to the first element in the array with value 50
how are always passing by valuing and using pointers to emulate pass by reference.
void IncrementPtr (int **p) {
insert code here
}
int A[3] = {50, 60 , 70};
int * q = A;
q = IncrementPtr(&q);
*p = *p+1;
void copy (char Sto[]. char sFrom[]) {
sTo= sFrom;
}.
void * malloc (size + t_size);
void free( void *ptr);
char * name = malloc(6);
strcpy (name, “CSE30”);
printf(“%s\n”, name);
remember that a string “CSE30 has 5 chars plus a final null terminating
C S E 3 0 \n
LDR R4, [R2, #8]
Mem to Reg=1 Mem to Write = 0 Reg Write = 1 ALU src = 1 (uses immediate offset) REgSrc = (does RD1 need to be data from R15(PC) or Rn)? Rn so (_0) , Does RD2 need to be data from Rd or 3:0? Doesn't matter, since SrcB will choose immeate to go to ALu we don't need RD2 tobecome writedata for memory so X, (X0)
11100101100100100100000000001000
LDR R4, [R2, R8]
Rd Rn Rm
Rn (19:16) 0010
Rd (15:12) 0100
Rm(3:0) 1000
Does this instruction take data read from memory or output to ALU? MEMORY
MemtoReg=1
Does insturction write to memroy ? No 0
MemtoWrite = 0
Does this instruction use an immediate offset? No
ALUSrc = 0
Does it write to register file? yes
RegWRite = 1
Does RD1 need to be data from r15 (PC) or Rn? Rn =0
RegSrc _ 0
Does RD2 need to be data from Rd or Rm? Rm = 0
RegSrc = 0 0
11100111100100100100000000001000
STR R4, [R2, #8]
Rd Rn Rm
Rn (19:16) 0010
Rd (15:12) 0100
Rm(11:0) 1000
Does this instruction use an immediate offset? YES
ALUSrc = 1
Does insturction write to memroy ? Yes 1
MemtoWrite = 1
Does it write to register file? No
RegWRite = 0
Does this instruction take data read from memory or output to ALU? We doon’t care whether themux on the far right takes data from memory or the output of hte ALU because we won’t be using it and Regwrite=0. so we wouldn’t b writing it to registers anyways
MemtoReg = X
Does RD1 need to be data from r15 (PC) or Rn? Rn =0
RegSrc _ 0
Does RD2 need to be data from Rd or Rm? Rd, 1
RegSrc = 1 0
Even though the mux before the ALU won’t select it to go to the ALU, RD2 still also goes into Data memory as Write Data (the data to store in memory)
.
STR R4, [R2, #8]
Rd Rn Rm
Rn (19:16) 0010
Rd (15:12) 0100
Rm(11:0) 1000
Does this instruction use an immediate offset? YES
ALUSrc = 1
Does insturction write to memroy ? Yes 1
MemtoWrite = 1
Does it write to register file? No
RegWRite = 0
Does this instruction take data read from memory or output to ALU? We doon’t care whether themux on the far right takes data from memory or the output of hte ALU because we won’t be using it and Regwrite=0. so we wouldn’t b writing it to registers anyways
MemtoReg = X
Does RD1 need to be data from r15 (PC) or Rn? Rn =0
RegSrc _ 0
Does RD2 need to be data from Rd or Rm? Rd, 1
RegSrc = 1 0
Even though the mux before the ALU won’t select it to go to the ALU, RD2 still also goes into Data memory as Write Data (the data to store in memory)
.
1110010110000010010000000001000
Convert the following machine instructions (in hex) into ARM assembly.
0xe503403c
Solution
Fields: 1110 01 0 1 0 0 0 0 0011 0100 0000 0011 1100
I = 0, P =1, U = 0, B = 0, W = 0, L = 0
STR R4, [R3, #-60]
For any LDR/STR we’ve done in this class, it’s used the syntax above, which uses pre-indexing (applies offset to Rn before loading storing). push/pop are the only instructions we have gone over that do write back. W=0 here because it does not write back to the base register (Rn). U=0 means our offset is negative. B=0 since we are loading one word, not one byte. I=0 means our offset is an immediate, not a register
Convert the following ARM instructions to machine code. Write your answer in HEX.
LDR r8, [r13, #8]
Rn = r13, Rd = r8, offset = 8
L = 1, B = 0, I = 0, P =1, W = 0 U = 1
Fields: 1110 01 0 1 1 0 0 1 1101 1000 0000 0000 1000
1110 0101 1001 1101 1000 0000 0000 1000 => 0xe59d8008
For any LDR/STR we’ve done in this course, it’s uses the syntax above, which uses pre-indexing (applies offset to Rn before loading storing). push/pop are the only instructions we have gone over that do write back. W=0 here because it does not write back to the base register (Rn). U=1 since our offset is positive. B=0 since we are loading one word, not one byte. I=0 since our offset is an immediate
Convert the following ARM instructions to machine code. Write your answer in HEX.
ADD r4, r5, r6
Rn = r5, Rd = r4, offset = r6
Fields: 1110 00 0 0100 0 0101 0100 00000 00 0 0110
1110 0000 1000 0101 0100 0000 0000 0110 => 0xe0854006
Rn = r5, Rd = r4, offset = r6
Fields: 1110 00 0 0100 0 0101 0100 00000 00 0 0110
1110 0000 1000 0101 0100 0000 0000 0110 => 0xe0854006
int * arr1 = malloc (8);
int arr2[2];
What do these two statements do?
They both declare integer arrays of size 2
arr2 is stored on stack
arr1 is stored on heap
Dereference operator : ->
• Easier to read and equivalent to (*p).
struct point { int xCoor; int yCoor;
};
void PrintPoint(struct point *p){
printf(“x is %d\n”, p->xCoor);
printf(“x is %d\n”, (*p).xCoor); }
struct point {
int xCoor;
int yCoor;
};
void PrintPoint(struct point *p){
printf(“x is %d\n”, p->xCoor);
printf(“x is %d\n”, (*p).xCoor); }Structs can be in data segment, stack or heap
typedef struct p {
int y;
char x;
} p_t; // this line gives the name to the type
p_t sp;
p_t is type
Using typedef can allow you to avoid having to type “struct” all the time.
Dangling pointer: Pointer points to a memory location that no longer exists
• Memory leaks (tardy free) Memory in heap that can no longer be accessed
MEmory leaks
Dangling Reference is when pointer still pointing to memory that has been reallocated
Memory leaks are memory that has not be free and still being “occupied”
int * f2 (int num){
int mem2[num];
return (mem2);
}
why is this bad? for memory management … creating a pointer that will get lost?
Examples of dangling pointer
A. void foo(int bytes) {
char *ch =(char *) malloc(bytes);
. . . . //unrelated to ch
}
C. char* foo(int bytes) {
char *ch =(char *) malloc(bytes);
return (ch);
}
Set a ptr to NULL after freeing it, to limit future segfaults
.
Lecture 8 : Introduction to ARM instructions and logic tables
.
