Structure and Function of the Processor

Question 1

What is the function of the ALU (Arithmetic Logic Unit)

Answer 1

Performs all of the processor’s Logical and Arithmetic operations

Question 2

Give examples of Logical Operations

Answer 2

AND, OR, NOT, NAND, NOR, XOR

Question 3

Give examples of Arithmetic Operations

Answer 3

Addition or Subtraction on Fixed or Floating Point numbers

Question 4

What is the function of the Control Unit?

Answer 4

Monitors communications between Hardware in the computer

Question 5

What are the Control Unit’s jobs?

Answer 5

Decoding Instructions
Storing the resulting data back in memory
Accepting the next instruction

Question 6

What are Registers?

Answer 6

Small memory cells that temporarily store data.
All arithmetic, logical and shift operations occur within registers

Question 7

Give examples of the CPU’s registers

Answer 7

Program Counter (PC)
Accumulator (ACC)
Memory Address Register (MAR)
Memory Data Register (MDR)
Current Instruction Register (CIR)

Question 8

What is the function of the Program Counter (PC)?

Answer 8

Holds the address of the next instruction to be executed

Question 9

What is the function of the Accumulator (ACC)?

Answer 9

Stores the results of ALU calculations

Question 10

What is the function of the Memory Address Register (MAR)?

Answer 10

Holds the address of a location to be read from/written to

Question 11

What is the function of the Memory Data Register (MDR)?

Answer 11

Temporarily stores the data that has been read/needs to be written to from the address in the MAR

Question 12

What is the function of the Current Instruction Register (CIR)?

Answer 12

Holds the current instruction to be executed

Question 13

What are Buses?

Answer 13

A set of parallel wires which connect two or more components in the CPU so that they can transfer data.
The number of bits that can be transferred simultaneously is to increase the Width of the wire.

Question 14

What are the 3 buses inside the CPU?

Answer 14

Data, Address and Control

Question 15

What is the function of the Data Bus?

Answer 15

Transports data and instructions between components.
Bi-directional

Question 16

What is the function of the Address Bus?

Answer 16

Transmits the memory addresses specifying where data is to be sent to or retrieved from. Uni-directional

Question 17

What is Assembly Code?

Answer 17

A simplified way of representing machine code using mnemonics. Structured using Opcode and Operand.
(i.e., ADD represents addition, LDA represents load)

Question 18

What is Opcode in Assembly Language?
(Operation Code)

Answer 18

Represents the type of instruction to be executed.
(ADD, LDA, STA, BRP, BRN, etc)

Question 19

What is Operand in Assembly Language?

Answer 19

Contains the address of the data that will have an operation performed

for example: ADD 5 (5 is the operand)

Question 20

What is the purpose of Addressing Mode in Assembly Language?

Answer 20

Specifies how the Operand is used

Question 21

What is Pipelining?

Answer 21

The process of completing the Fetch, Decode, Execute cycle of three separate instructions simultaneously, holding the appropriate data in a buffer in close proximity to the CPU until its needed.

Whilst one instruction is being executed, another is being decoded and another fetched.

Question 22

What is Instruction Pipelining?

Answer 22

Divides incoming instructions into a series of sequential steps performed by different processor units.
Different parts of instructions are processed in parallel

Question 23

Explain the Fetch, Decode, Execute cycle.

Answer 23

Address from PC is copied into MAR.
Instruction from address is copied into MDR by Data Bus.
PC increments by 1.
The value held in MDR copied into CIR.

Contents of CIR split into Opcode and Operand.

Decoded instruction is executed.

Question 24

What are the 3 main factors that affect CPU performance?

Answer 24

Clock Speed
Number of Cores
Amount and Type of Cache memory

Question 25

What is a CPU’s Clock Speed?

Answer 25

The time it takes for one clock cycle to complete (0 to 1)

Each CPU operation starts as the clock changes from 0 to 1. The higher the clock speed, the more operations per second (Hz).

Question 26

Why do Cores affect CPU performance?

Answer 26

A core is an independent processor that is able to run its own fetch-decode-execute cycle. This means that a computer with multiple cores can complete more than one F-E-D cycle at any given time.

A computer with 2x as many cores than another is theoretically 2x as fast, however not all programs are able to utilise multiple cores.

Question 27

Why does Cache size and type affect CPU performance?

Answer 27

Cache is the CPU’s onboard memory. Instructions fetched from main memory are copied to cache so that they can be accessed quicker if needed. As cache fills up, unused instructions are replaced.

Question 28

What are the properties of Level 1 Cache?

Answer 28

Very Fast
Small Capacity (2-64KB)

Question 29

What are the properties of Level 2 Cache?

Answer 29

Relatively fast
Medium Capacity (256KB-2MB)

Question 30

What are the properties of Level 3 Cache?

Answer 30

Slow compared to other levels
Large Capacity

Question 31

What is Von Neumann computer architecture?

Answer 31

Basic components and processor (control unit, registers and memory units)

Shared data and memory bus for both instructions and data.

Question 32

What is Harvard computer architecture?

Answer 32

Separate physical memory for instructions and data.

Question 33

What are the advantages of Von Neumann computer architecture?

Answer 33

Cheaper to develop
Control unit is easier to design
Programs can be optimised in size

Question 34

What are the advantages of Harvard computer architecture?

Answer 34

Quicker execution as data and instruction can be fetched in parallel
Memories can be different sizes - makes more efficient use of space.

Question 35

What is Contemporary Processing in computer architecture?

Answer 35

A combination of Harvard and Von Neumann.
Uses Von Neumann when working with data and instructions in main memory.
Uses Harvard to divide the cache into instruction cache and data cache.

Question 36

The 3 computer architectures

Answer 36

Von Neumann
Harvard
Contemporary