SLR 1: Structure and Functions of the Processor

Question 1

Function of Control Unit?

Answer 1

. Coordinates all activities in cpu
. Directs flow of data between CPU and other devices
. Accepts next instruction, decodes it, handles its ecectutions and stores data in registers
. Sends memory read and write requests to main memory on the control bus

Question 2

Function of the Program Counter?

Answer 2

. Holds address of the next instruction to be executed
. At the start of the FDE the address in the PC is copied to the MAR

Question 3

Function of the MAR?

Answer 3

. Holds address of memory location in which data or instruction is about to be fetched from or written to
. Sends address to memory down the address bus

Question 4

Function of MDR?

Answer 4

. Used to temporarily stort data which is read from or written to memory
. all data to and from memory must travel through the data bus and through the MDR

Question 5

Function of the CIR?

Answer 5

. Holds the current instruction being executed
. Contents of the MDR are copeied to the Cir is its an instruction
. Contains the opcode and operand of the current instruction

Question 6

Function of the ALU?

Answer 6

. Performs arethmatic and logical operations on data
. Boolean logic operations
. Often uses general purpose registers to temporarily hold result of a calculation (eg ACC)
. Conduit for input and output

Question 7

Function of the ACC?

Answer 7

. one of the general purpose registers
. data or control info is stored in them
. more general purpose operators a processer has, the faster it’ll operate
. ALU Calculations are temporarily stored here

Question 8

Benefits of Pipelining

Answer 8

The CPU is never idle
No latency between each step of FDE.

Question 8

What is pipelining?

Answer 8

Pipelining is when different instructions can be fetched decoded and executed concurrently.

Question 9

What are the features of the Von Neumann Architecture?

Answer 9

. shared memory for instructions + data
. I + D are stored in the same format
. A single CU or processor follows a linear FDE
. One I at a time
. Registers are used for fast access to I + D

Question 10

What is SIMD?

Answer 10

Single Instruction Multiple Data - parallel processing is where a processor carries out one instruction on multiple pieces of data.

Question 11

What are the features of a Harvard Architecture?

Answer 11

. Instructions + Data stored in separate memory units
. I + D each have their own bus
. Pipelining is possible
. Used in RISC Processors

Question 12

What is SIMD often used in?

Answer 12

GPU

Question 13

What is MIMD?

Answer 13

Multiple Instructions Multiple Data - Multiple Instructions are used across many pieces of data.

Question 14

What factors effect the performance of the CPU?

There’s 4.

Answer 14

Clock Speed
Cache Size
No of Cores
Bus Width

Question 15

What is cache size and why is it useful?

Answer 15

Temporary Storage of data and instruction read from and written to.

Much quicker access than RAM.

Question 16

What is a core?

Answer 16

Each core has its own registers, ALU, ACC and CU. Dual core CPU have capabilities to run two processes simultaneously if they are paralyzable.

Question 17

What is clock speed?

Answer 17

The number of instructions executed per second.

Question 18

What happens in the fetch cycle?

Answer 18

. PC is checked, it holds address of next I to be Executed
. PC Copied to MAR
. Sent along A - Bus to RAM.
. CU sends read signal to RAM.
. Contents of that address are now sent along D-Bus to MDR.
. MDR copied to CIR
. PC increments

Question 19

What happens in the decode stage of the FDE?

Answer 19

. Data in the CIR is split into opcode and operand
. It is decoded by the decode unit

Question 20

What is opcode and operand?

Answer 20

Opcode - What process to do to some data/address.
Operand - What do do that process to.

Question 21

What do each of the buses do?

Answer 21

Address Bus: Carries memory addresses
Data Bus: Carries the binary that make up the data carried.
Control Bus: Carries control signals (Read/Write) to other CPU components.