SLR 1: Structure and Functions of the Processor Flashcards
Function of Control Unit?
. Coordinates all activities in cpu
. Directs flow of data between CPU and other devices
. Accepts next instruction, decodes it, handles its exectutions and stores data in registers
. Sends memory read and write requests to main memory on the control bus
Function of the Program Counter?
. Holds address of the next instruction to be executed
. At the start of the FDE the address in the PC is copied to the MAR
Function of the MAR?
. Holds address of memory location in which data or instruction is about to be fetched from or written to
. Sends address to memory down the address bus
Function of MDR?
. Used to temporarily stort data which is read from or written to memory
. all data to and from memory must travel through the data bus and through the MDR
Function of the CIR?
. Holds the current instruction being executed
. Contents of the MDR are copeied to the Cir is its an instruction
. Contains the opcode and operand of the current instruction
Function of the ALU?
. Performs arethmatic and logical operations on data
. Boolean logic operations
. Often uses general purpose registers to temporarily hold result of a calculation (eg ACC)
. Conduit for input and output
Function of the ACC?
. one of the general purpose registers
. data or control info is stored in them
. more general purpose operators a processer has, the faster it’ll operate
. ALU Calculations are temporarily stored here
Benefits of Pipelining
The CPU is never idle
No latency between each step of FDE.
What is pipelining?
Pipelining is when different instructions can be fetched decoded and executed concurrently.
What are the features of the Von Neumann Architecture?
. shared memory for instructions + data
. I + D are stored in the same format
. A single CU or processor follows a linear FDE
. One I at a time
. Registers are used for fast access to I + D
What is SIMD?
Single Instruction Multiple Data - parallel processing is where a processor carries out one instruction on multiple pieces of data.
What are the features of a Harvard Architecture?
. Instructions + Data stored in separate memory units
. I + D each have their own bus
. Pipelining is possible
. Used in RISC Processors
What is SIMD often used in?
GPU
What is MIMD?
Multiple Instructions Multiple Data - Multiple Instructions are used across many pieces of data.
What factors effect the performance of the CPU?
There’s 4.
Clock Speed
Cache Size
No of Cores
Bus Width
What is cache size and why is it useful?
Temporary Storage of data and instruction read from and written to.
Much quicker access than RAM.
What is a core?
Each core has its own registers, ALU, ACC and CU. Dual core CPU have capabilities to run two processes simultaneously if they are paralyzable.
What is clock speed?
The number of instructions executed per second.
What happens in the fetch cycle?
. PC is checked, it holds address of next I to be Executed
. PC Copied to MAR
. Sent along A - Bus to RAM.
. CU sends read signal to RAM.
. Contents of that address are now sent along D-Bus to MDR.
. MDR copied to CIR
. PC increments
What happens in the decode stage of the FDE?
. Data in the CIR is split into opcode and operand
. It is decoded by the decode unit
What is opcode and operand?
Opcode - What process to do to some data/address.
Operand - What do do that process to.
What do each of the buses do?
Address Bus: Carries memory addresses
Data Bus: Carries the binary that make up the data carried.
Control Bus: Carries control signals (Read/Write) to other CPU components.
