[Semester 1] Combinational Logic Flashcards

1
Q

Where might you find an adder?

A

In the Arithmetic Logic Unit (ALU); it’s used to add numbers together (hence the name!)

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2
Q

Sum

A

The total of the numbers being added. It’s true if only one input is true.

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3
Q

Carry

A

Anything that needs to be carried over during addition

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4
Q

True or false: Carry is only true if all inputs are true

A

Both! This is true in a half adder but in a full adder, only one input (one of the AND gates) has to be true.

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5
Q

Delay

A

How long a circuit takes to calculate an output

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6
Q

Look Ahead Carry

A

Looks at lower bits to see whether a higher carry will be generated

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7
Q

Why does the delay in a Ripple Carry adder increase with each adder?

A

An adder can’t calculate sum and carry until it receives the carry from the previous adder.

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8
Q

Comparator

A

Compares two currents and uses the largest one

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9
Q

Multiplexer (mux)

A

Selects an output based on what the majority of input signals are equal to

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10
Q

Control signal

A

Decides which input signal to use for the circuit’s output

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11
Q

True or false: The more input signals there are, the more control signals needed.

A

True! If a mux has 8 input signals for example, it will need 3 control signals in order to create 8 possible combinations.

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12
Q

Encoder

A

Converts multiple input signals into a single output

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13
Q

Decoder

A

Converts instructions into signals, which are then sent around the CPU.

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14
Q

In a decoder, how many outputs can be activated at once?

A

1, as shown in this truth table: https://b3van8qm1o7ou9d3b48qdhsg-wpengine.netdna-ssl.com/wp-content/uploads/2020/11/VHDL-Table-1.jpg (sorry for the link i have to pay to put photos in here)

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15
Q

Demultiplexer

A

Uses input signals to create several outputs

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16
Q

True or false: A demultiplexer is almost identical to a multiplexer

A

False! A demultiplexer’s layout is more similar to that of a decoder, but with an extra input signal.

17
Q

Identity law

A

Output is always equal to input A.
AND: 1A = A
OR: 0 + A = A

18
Q

Null law in AND form

A

Output is always 0.

0A = 0

19
Q

Null law in OR form

A

Output is always 1.

1 + A = 1

20
Q

Idempotent law

A

If all inputs are A, the output will also be A.
AND: AA = A
OR: A + A = A

21
Q

Inverse law in AND form

A

If one input is the negation of the other input, the output will be 0.
AĀ = 0

22
Q

Inverse law in OR form

A

If one input is the negation of the other input, the output will be 1.
A + Ā = 1

23
Q

Commutative law

A

Order of inputs isn’t important.
AND: AB = BA
OR: A + B = B + A

24
Q

Associative law

A

If there are 3 inputs, order isn’t important.
AND: (AB)C = A(BC)
OR: (A + B) + C = A + (B + C)

25
Q

Absorption law

A

Input and output must be the same value
AND: A(A + B) = A
OR: A + AB = A

26
Q

De Morgan’s Law

A

Negation of AND = negation of OR

A̅ +̅ B̅ = A̅B̅