Reference 1

Question 1

Calculate the value of the physical address that follows. Assume all number as hexadecimal numbers.

A. A32CFH; C2612
B. A33CEFH; C2513
C. A31CFH; C2512
D. A34CDH; C2112

Answer 1

A32CFH; C2612

Question 2

A pipeline lowers the performance because no work is done during the ___

Answer 2

Stall

Question 3

Intel has embraced the newer EPIC philosophy. What does EPIC stand for?

Answer 3

Explicitly Parallel Instruction Computing

Question 4

When FXCH is executed in parallel with another floating-point instruction, how many clock cycles are required for its execution?

Answer 4

0

Question 5

The hit ratio affects the ___ access time.

Answer 5

Average

Question 6

An attempt is made to keep instructions completing at a rate of ___ per clock cycle.

Answer 6

One

Question 7

What are the two important factors in determining power consumption of a processor?

Answer 7

Clock speed and operating voltage

Question 8

How many parity bit/s there is for every 8 bytes of data (a quarter of a line) in the instruction cache?

Answer 8

1

Question 9

Fill out the blank: ___ plays an important role in helping a CISC or RISC machine because this re-arranges certain pairs of instructions to allow them to execute in parallel in the floating-point

Answer 9

Compiler

Question 10

A __ stored with the entry is compared with the remaining address bits.

Answer 10

Tag

Question 11

This method is used in writing to the cache and to main memory.

Answer 11

Writethrough

Question 12

For the direct-mapped cache organization, indicate all its field with their name and size in bits. Assume a main memory size of 4 Gigabytes & a cache memory capacity of 64 kilobytes of main memory data. Compute the total capacity of the cache memory.

Answer 12

16 bits

Question 13

What formula is used to predict the average access time?

Answer 13

Tacc = HitRatio x Tcache + 1( 1 – HitRatio ) x ( Tcache + Tram )
+-+

Question 14

Bypass 1 connects the output of the __ stage to the input of the __ stage.

Answer 14

X1, EX

Question 15

It builds the schedule of condition-test, true and false instructions, and sets the predicate flags.

Answer 15

Compiler

Question 16

Which of the following is not intended for personal computing processors

Answer 16

Xeon

Question 17

What is the Intel’s first sixth-generation processor?

Answer 17

Pentium Pro

Question 18

The MMX Technology added to the Pentium processes have a total of __ new instructions.

Answer 18

57

Question 19

What will happen if you lower the clock frequency?

Answer 19

Decrease in performance

Question 20

Which of the processors has no level 2 cache?

Answer 20

Celeron

Question 21

Processors capable of parallel instruction execution of multiple instructions

Answer 21

Superscalar machine

Question 22

These instructions allow the programmer to convert between integer and floating-point numbers, as well as perform floating-point reciprocal and square root.

Answer 22

SIMD-FP

Question 23

These instructions give the programmer ways to organize data for SIMD computations

Answer 23

New media

Question 24

This allows use of minimal logic in each stage and a higher clock speed for the pipeline

Answer 24

Hyper-pipelined technology

Question 25

The Pentium’s mechanism for maintaining cache coherency in its data cache is called MESI (modified/exclusive/shared/invalid). Which is the definition of the Exclusive state?

Answer 25

The current line has not been modified (matches main memory) and is only available in a single cache. Writing to this line changes its state to modified.