Processors and the Fetch-Decode-Execute Cycle Flashcards
Accumulator
Stores the result of the ALU’s most recent operation
Arithmetic Logic Unit
Performs all of the CPU’s arithmetic and logical functions
Cache Memory
Low-capacity, high-speed memory that stores frequently used instructions and data
CISC
Instruction set where different instructions may require a different number of fetch–decode–execute cycles to run
Clock Speed
Frequency at which the CPU can carry out operations
Core
Processor within a CPU which can run a single instruction at a time
Current Instruction Register
Holds the instruction that the CPU is currently executing
Fetch-Decode-Execute Cycle
Sequence that is constantly repeated by the computer in order to carry out instructions
Harvard Architecture
Computer architecture where data and instructions are stored in separate locations
Instruction Set
List of all machine code commands that are recognised by a particular CPU
Memory Address Register
Holds the memory address that needs to be accessed
Memory Data Register
Holds the data that has just been loaded from, or is about to be saved to, memory
Multicore System
Computer that uses multiple processors
Opcode
Part of machine instructions that specifies the operation to be performed
Operand
Part of machine instructions that specifies the value to be used
Parallel System
Computer system that can carry out multiple operations simultaneously
Pipelining
Technique for implementing instruction-level parallelism within a single processor in order to improve performance
Program Counter
Register that is incremented in each iteration of the fetch–decode–execute cycle
Register
Low-capacity storage locations within the CPU that are used in the fetch–decode–execute cycle
RISC
Instruction set where different instructions require the same number of fetch–decode–execute cycles to run
Von Neumann Architecture
Computer architecture based on the stored-program computer concept; data and instructions are stored together
