Processor Microarchitecture Flashcards
What is microarchitecture?
the specific arrangement of registers, ALUs, FSMs, memories and other logic building blocks needed to implement an architecture
What are the two interacting parts of the microarchitecture?
Datapath - made up of memories, registers, ALUs and multiplexers and operates in 32-bit words of data.
Control unit - produces signals to control the operation of the datapath. It receives the current instruction and tells the datapath how to execute it.
What are two of the microarchitectures for ARM achitecture?
Single-cycle: each instruction executes in a single cycle
Pipelined: each instruction is broken up into a series of steps and multiple instructions execute at once
What is execution time?
Measure of performance for microarchitecture. Execution time = (#instructions)(cycles/instruction)(secs/cycle)
What is CPI?
cycles/instruction
what is clock period?
seconds/cycle
What is IPC
instructions/cycle
Name the ARM architectural state elements
- PC
- status register
- instruction memory
- register file
- data memory
Program counter:
- part of the register file but it is read and written every cycle, independent of the register file
- the output points to the address of the current instruction
- the input points to the address of the next instruction
Instruction memory:
- receives a 32-bit instruction address at input A and reads the 32-bit instruction from that address into RD
Register File:
- two read ports, A1 and A2. The 4 bit addresses on these ports are used to select register operands. The 32-bit data from these registers are read to RD1 and RD2
- 4-bit address on A3 specifies register which data at WD3 is written to, given WE3 is asserted
- R15 gives PC+8
Data memory:
- single read/write port
- if WE is asserted, data at WD is written to address A
- if WE isn’t asserted, data at address A is read to port RD
What are the main parts of the control unit?
Decoder: generates the control signal for a particular instruction
Conditional logic: maintains status flags. Only enables update to architectural state when instruction should be conditionally executed
What are the sub sections of the decoder?
- PC Logic: checks if instruction is a write to R15 or a branch
- Main Decoder: determines type of instruction (e.g. STR, DP, B) and produces appropriate control signal to the datapath
- ALU Decoder: chooses ALUcontrol based on type of instruction (ADD, SUB, AND)
What does conditional logic do in the control unit?
- checks if instruction should execute (if not, force PCSrc, RegWrite and MemWrite to 0)
- possible update status register (Flags 3:0)
Latency
time to execute one instruction
Throughput
how many instructions can be completed per unit time
What are the five stages of a pipelined ARM processor?
- Fetch
- Decode
- Execute
- Memory
- Writeback
Fetch stage:
processor reads instruction from memory
Decode stage:
processor reads source operands from the register file and decodes the instruction to produce control signals
Execute stage:
computation in current instruction is performed using ALU
Memory stage:
processor reads or writes data to memory
Writeback stage:
the processor writes the result to the register if applicable
Explain the process a pipelined ARM processor carries out for each instruction
It is broken up into 5 stages: - - Fetch: processor reads instruction from memory.
- Decode: processor reads source operands from the register file and decodes the instruction to produce control signals.
- Execute: computation in current instruction is performed using ALU.
- Memory: processor reads or writes data to memory.
- Writeback: the processor writes the result to the register if applicable
