Processor Microarchitecture

Question 1

What is microarchitecture?

Answer 1

the specific arrangement of registers, ALUs, FSMs, memories and other logic building blocks needed to implement an architecture

Question 2

What are the two interacting parts of the microarchitecture?

Answer 2

Datapath - made up of memories, registers, ALUs and multiplexers and operates in 32-bit words of data.
Control unit - produces signals to control the operation of the datapath. It receives the current instruction and tells the datapath how to execute it.

Question 3

What are two of the microarchitectures for ARM achitecture?

Answer 3

Single-cycle: each instruction executes in a single cycle

Pipelined: each instruction is broken up into a series of steps and multiple instructions execute at once

Question 4

What is execution time?

Answer 4

Measure of performance for microarchitecture. Execution time = (#instructions)(cycles/instruction)(secs/cycle)

Question 5

What is CPI?

Answer 5

cycles/instruction

Question 6

what is clock period?

Answer 6

seconds/cycle

Question 7

What is IPC

Answer 7

instructions/cycle

Question 8

Name the ARM architectural state elements

Answer 8

• PC
• status register
• instruction memory
• register file
• data memory

Question 9

Program counter:

Answer 9

• part of the register file but it is read and written every cycle, independent of the register file
• the output points to the address of the current instruction
• the input points to the address of the next instruction

Question 10

Instruction memory:

Answer 10

• receives a 32-bit instruction address at input A and reads the 32-bit instruction from that address into RD

Question 11

Register File:

Answer 11

• two read ports, A1 and A2. The 4 bit addresses on these ports are used to select register operands. The 32-bit data from these registers are read to RD1 and RD2
• 4-bit address on A3 specifies register which data at WD3 is written to, given WE3 is asserted
• R15 gives PC+8

Question 12

Data memory:

Answer 12

• single read/write port
• if WE is asserted, data at WD is written to address A
• if WE isn’t asserted, data at address A is read to port RD

Question 13

What are the main parts of the control unit?

Answer 13

Decoder: generates the control signal for a particular instruction
Conditional logic: maintains status flags. Only enables update to architectural state when instruction should be conditionally executed

Question 14

What are the sub sections of the decoder?

Answer 14

• PC Logic: checks if instruction is a write to R15 or a branch
• Main Decoder: determines type of instruction (e.g. STR, DP, B) and produces appropriate control signal to the datapath
• ALU Decoder: chooses ALUcontrol based on type of instruction (ADD, SUB, AND)

Question 15

What does conditional logic do in the control unit?

Answer 15

• checks if instruction should execute (if not, force PCSrc, RegWrite and MemWrite to 0)
• possible update status register (Flags 3:0)

Question 16

Latency

Answer 16

time to execute one instruction

Question 17

Throughput

Answer 17

how many instructions can be completed per unit time

Question 18

What are the five stages of a pipelined ARM processor?

Answer 18

• Fetch
• Decode
• Execute
• Memory
• Writeback

Question 19

Fetch stage:

Answer 19

processor reads instruction from memory

Question 20

Decode stage:

Answer 20

processor reads source operands from the register file and decodes the instruction to produce control signals

Question 21

Execute stage:

Answer 21

computation in current instruction is performed using ALU

Question 22

Memory stage:

Answer 22

processor reads or writes data to memory

Question 23

Writeback stage:

Answer 23

the processor writes the result to the register if applicable

Question 24

Explain the process a pipelined ARM processor carries out for each instruction

Answer 24

It is broken up into 5 stages: - - Fetch: processor reads instruction from memory.

• Decode: processor reads source operands from the register file and decodes the instruction to produce control signals.
• Execute: computation in current instruction is performed using ALU.
• Memory: processor reads or writes data to memory.
• Writeback: the processor writes the result to the register if applicable

Question 25

Two types of pipelined hazards:

Answer 25

Data hazard: register value not yet written back to register file
Control hazard: next instruction not decided yet (caused by branch)

Question 26

Handling data hazards:

Answer 26

• insert NOPs in code at compile time
• rearrange code at compile time
• forward data at run time
• stall the processor at run time

Question 27

What is data forwarding, how does it work?

Answer 27

• It is a method of handling data hazards
• Hazard unit checks if register read in execute stage matches register written in memory/writeback stage, if so forwards result

Question 28

What is the problem with inserting NOPs to mitigate data hazards?

Answer 28

It wastes cycles and processor time

Question 29

What is stalling? How does it work?

Answer 29

• It is a method of handling data hazards
• Hazard unit checks if either source register in the decode stage matches the one being written in the execute stage
• If so, hazard unit enables stall, flushing initial value in source operand and repeating decode instruction with correct register values

Question 30

Why does branching cause control hazards?

Answer 30

• branch not determined until writeback stage of pipeline
• instructions after branch fetched before branch occurs
• these 4 instructions must be flushed if branch happens

Question 31

Branch misprediction penalty:

Answer 31

• number of instructions flushed when branch is taken

Question 32

How is branch misprediction penalty cut from 4 to 2 when branch instruction occur occur?

Answer 32

By adding a branch multiplexer before PC register to select BTA from ALU result in execute stage. The conditional unit controls this multiplexer, it is only asserted when branch is taken