Memory

Question 1

What are the three levels in the memory hierarchy

Answer 1

Cache, main memory, virtual memory

Question 2

Temporal locality

Answer 2

• locality in time

- keeps recently accessed data in higher levels of memory hierarchy

Question 3

Spatial Locality

Answer 3

• locality in space

- when data is accessed, nearby data brought into higher levels of memory hierarchy too

Question 4

Hit:

Answer 4

data found in that level of memory hierarchy

Question 5

Miss:

Answer 5

data not found in that level of memory hierarchy (must go to next level)

Question 6

Hit rate:

Answer 6

hits/#memory accesses (1 minus miss rate)

Question 7

Miss rate:

Answer 7

misses/#memory accesses (1 minus hit rate)

Question 8

Average Memory Access Time (AMAT):

Answer 8

average time for processor to access data. Given by:

tcache + MRcache(tMM + MRMM(tVM))

Question 9

Cache:

Answer 9

• highest level of memory

- fast (about 1 cycle access time)

Question 10

What is Capacity (C):

Answer 10

number of data bytes in cache

Question 11

What is block size (b):

Answer 11

bytes of data brought into cache at once

Question 12

What is number of Blocks (B):

Answer 12

number of blocks in cache (B = C/b)

Question 13

What is Degree of associativity (N)

Answer 13

number of blocks in a set

Question 14

How do you calculate number of sets in cache?

Answer 14

S = B/N

Question 15

three types of cache organisation:

Answer 15

• Direct mapped (1 block per set)
• N-way set associative (N blocks per set)
• Fully associative (all cache blocks in one set)

Question 16

How do larger blocks in direct mapped cache improve performance?

Answer 16

reduce compulsory misses though spatial locality

Question 17

How does associativity improved cache performance?

Answer 17

reduces conflict misses

Question 18

What are the different types of misses?

Answer 18

• compulsory: first time data accessed
• capacity: cache too small to hold all data of interest
• conflict: data of interest maps to same location in cache

Question 19

Miss penalty:

Answer 19

time it takes to retrieve a block from lower level of hierarchy

Question 20

How are capacity misses reduced?

Answer 20

LRU replacement: least recently used block in a set is evicted

Question 21

What is page size? (VM)

Answer 21

amount of memory transferred from hard disk to DRAM at once

Question 22

What is address translation? (VM)

Answer 22

determining physical address from virtual address

Question 23

What is page table? (VM)

Answer 23

lookup table used to translate virtual addresses to physical addresses

Question 24

What are page table challenes?(VM)

Answer 24

• page table is large
• load/store requires 2 main memory accesses
• this cuts performance in half`

Question 25

What is a TLB and how does it work?

Answer 25

• Table Lookaside Buffer is a small cache of most recent translations
• speeds up address translation by reducing # of memory accesses for most loads/stores from 2 to 1
• small: accessed in <1 cycle
• fully associative
• > 99% hit rate
• however it can’t store many entries (16 - 512)

Question 26

How is memory protected in virtual memory?

Answer 26

Each process/program has its own page table with a unique virtual to physical page mapping. Each process can use the entire virtual address space.