Processor Architecture

Question 1

Von Neumann

Answer 1

. Instructions + Data stored in RAM
. Same data bus uses to transfer data and instructions
. Same word size is used for all memory
. Fetch instructions and fetch data tale 2 clock cycles
. Easy for the CU to manage processes
. More efficient use of RAM
. Only one data bus needed so it is cheaper

Question 2

Von Neumann Bottleneck

Answer 2

. Every piece or data and instruction has to pass across the data bus in order to move from main memory into the cpu
. This is a problem because data bus is alot slower than the rate at which the cpu can carry out instructions
. This is called von neumann bottleneck

Question 3

Harvard

Answer 3

. Separate memory for data and instructions so 2 data buses
. One can be read only and one write
. Word size can be different
. Buses will be different sizes
. Can be faster than von neumann as data and instructions can be fetched in parallel, only taking 1 clock cycle
. Memory may be wasted
. Expensive

Question 4

Other contemporary processor architecture

Answer 4

. Can incorporate elements from harvard and von neumann

Question 5

CISC

Answer 5

. Complex hardware
. Multiple clock cycles
. Greater energy consumption
. Expensive
. Can’t use pipelining
. Compiler has less work to do
. More efficient use of ram

Question 6

RISC

Answer 6

. Simpler hardware
. Single cycle per instruction
. Cheaper to produce
. Low energy consumption
. Supports pipelining
. Compiler has to do more work
. Heavy use of RAM