Pipelining Flashcards
What is pipelining
Pipelining is a technique used in computing and electronics to improve the efficiency and performance of a system by dividing a task into multiple smaller stages and processing those stages in parallel.
What can pipelining be related too
A factory, each stage of the pipeline performs a specific part of the task, and the stages are connected in a sequential manner, much like an assembly line in a factory.
What is instruction fetch IF
The processor retrieves the next instruction from memory and stores it in the instruction register (the location of the next task).
Key Components: Program Counter (PC), Memory Interface.
What is instruction decode ID
The instruction is decoded to determine the operation, source/destination operands, and immediate data.
What are the five common stages of a processor pipeline
- Instruction Fetch (IF)
- Instruction Decode (ID)
- Execute (EX)
- Memory Access (MEM)
- Write Back (WB)
What happens during the Execute (EX) stage
The actual operation (e.g., arithmetic, logic, branch) is performed using the ALU or branch units.
What happens during the Memory Access (MEM) stage
Data is fetched from or written to memory, as required by the instruction
What happens during the Write Back (WB) stage
The result of the instruction os written back to the destination (e.g., register of memory)
What is the role of the ALU in pipelining
The ALU performs the athletic and logical operations during the Execute (EX) stage
What is an example of an instruction broken into pipeline stages?
IF: Fetch the instruction.
ID: Decode the operation and operands.
EX: Add values in R2 and R3 using the ALU.
MEM: Not needed for this instruction.
WB: Write the result to R1.
What are pipelining hazards
Issues like data hazards, control hazards, and structural hazards that disrupt smooth pipeline execution.
What is a data hazard in pipelining
A situation where one instruction depends on the result of a previous instruction.
What is a control hazard in pipelining
A delay caused by changed in instruction flow, such as branches or jumps
What is a structural hazard in pipelining
When two or more stages compete for the same resource, causing a conflict.
What are some pipeline optimisation techniques
Branch prediction, hazard handling (e.g., forwarding, stalling), and pipeline registers/buffers.
What is branch prediction in pipelining
A technique to guess the outcome of a branch instruction to reduce control hazards.
What is the main benefit of pipelining
It increases instruction throughput by processing multiple instructions simultaneously.
What is a jump in a processor
A jump is an instruction that unconditionally changes the flow of execution to a different part of the program.
What is a branch in a processor
a conditional instruction that changes the flow of execution based on a condition
What is a conditional branch
A branch that changes the flow only if a specific condition is met (e.g., BEQ R1, R2, Label). E.g. in if or while statements
What is an unconditional branch
A branch that always changes the flow of execution, similar to a jump (e.g., B Label).
How are branches and jumps different
Branches can be conditional or unconditional.
Jumps are always unconditional.
Why do branches and jumps cause control hazards in pipelining?
They disrupt the normal sequential instruction flow, making it difficult to predict the next instruction.
What is branch prediction
A technique where the processor guesses the outcome of a branch to minimize delays caused by control hazards.
What is branch prediction in a processor
A technique where the processor guesses the outcome of a branch instruction (e.g., conditional jumps or function calls) before it is fully resolved.
Why is branch prediction important?
It allows the processor to decide whether to follow a branch (jump to another part of the code) or continue with the next sequential instruction, reducing pipeline stalls.
What is a static branch predictor?
A branch predictor that makes fixed predictions based on a simple rule without considering runtime behavior.
What are common techniques used in static branch prediction?
Always predict “taken.”
Always predict “not taken.”
Predict backward branches (loops) as taken.
What is a hybrid branch predictor?
A predictor that combines multiple branch prediction techniques to improve accuracy.
What is an example of a hybrid branch predictor?
The Tournament Predictor, which dynamically selects the best prediction strategy for each branch.
What is speculative execution
A performance optimization technique where the processor guesses the outcome of conditional operations and begins executing instructions ahead of time.
How does speculative execution avoid pipeline stalls?
By keeping the processor’s pipeline filled with instructions, minimizing idle time while waiting for branch or memory fetch decisions.
What happens if speculation is correct?
The results are committed to the processor’s architectural state, making them visible to software.
What happens if speculation is incorrect?
The pipeline is flushed, the speculative instructions are discarded, and the processor rolls back to the correct state before the branch.
What is out-of-order execution?
A technique where the processor executes instructions based on a data flow graph rather than program order, bypassing stalled instructions.
How does in-order execution differ from out-of-order execution?
In-order: Executes instructions in the exact sequence they appear. Delays in one instruction stall the entire pipeline.
Out-of-order: Executes instructions that are ready, bypassing stalled instructions.
What is the purpose of committing instructions in out-of-order execution?
To ensure the program maintains its intended semantics by committing results in order, even if instructions execute out-of-order.
What is the initial state of a 2-bit branch predictor?
The initial state is typically “10” (Weakly Taken).
What happens in speculative execution when encountering a branch-heavy loop
The processor guesses the outcome of the branch and begins executing the appropriate set of instructions, improving efficiency.
