Part 1 - Topic 2 & 3 - Synthesis and Testing / Programmable Logic Devices Flashcards
Whart is a netlist?
In electronic design, a netlist is a description of the connectivity of an electronic circuit. In its simplest form, a netlist consists of a list of electronic components in a circuit and a list of the nodes they are connected to.
Resource Sharing
A synthesis tool must recognise whether the physical resoures required to implement a complex behaviour can be shared.
If the data flow within the behaviour do not conflict, the resource can be shared between two or more paths.
What are static loops?
Give an example.
A loop is static if the number of iterations can be determined by the compiler before a simulation.
In other words, a static loop iterates for a fixed predetermined number of steps
What are non-static loops?
A nonstatic or data-dependent loop has a number of iterations which is dependent on the data.
In contrast to static loops, the iterations of a non-static loop must be separated by a synchronising edge-sensitive event control expression in order to be synthesised.
Write SystemVerilog code to implement the following function in hardware:
The apostrophes signify inverse.
Write a self-checking test bench for this function:
What is inertial delay?
Explain whats happening the image.
Inertial delay of a system is the time required for the system to recognise the changes in its input. So input changes will be reflected in the output if and only if the input remains stable more than inertial delay.
A proper answer to image still needed.
What is the minimum clock cycle time for the circuit?
What’s the problem with the ‘sensitive path algorithm’?
Why does finding a test for B/0 not work?
Does not handle reconvergent paths well
Set B to 1. To propagate the state of B to E requires A = 1.
To propagate the state of E to Z requires F = 0, which requires both A = 1 and B = 1.
But this isn’t possible if B is stuck at 0.
D Algorithm: What values do nodes in AND and OR gates needs to take to test a node?
To propagate through a AND gate the other node needs to be 1, so the other node determines the output.
With an OR gate the other node needs to be 0, because if the output node is changing you know it’s coming from the node you are testing.
FPGA vs ASIC
D Algorithm: How do you progate a value through a AND and OR gate respectively?
For AND the other value has to be 1.
For OR the other value has to be 0.
This makes sense because in both cases the node with value D determines the output of the gate.
D Algorithm: What do you do when a node being tested is connected to two gates?
You need to figure which node to propagate D through. Good chance one doesn’t work and leads to the node having to being either 0 or 1 for D to propagate to the end.
Write possible test pattern using D algorithm for d/0
Remember to show working…
Important conclusions to come to are that top AND needs to be used for propagation of D, middle AND gate needs to output 0 to allow for D to propagate through the top OR gate and bottom AND gate with D connected needs to output 0, which then gets inverted to 1, so that both OR gates output 0.
