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Microprocessor > Opcodes > Flashcards

Opcodes Flashcards

1
Q

Copy from source to destination

A

MOV

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2
Q

this instruction copies the contents of the source register into the destination register; the contents of the source register are not altered

A

MOV

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3
Q

Move immediate 8-bit

A

MVI

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4
Q

the 8bit data is stored in the destination register

A

MVI

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5
Q

Load accumulator

A

LDA

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6
Q

load accumulator indirect

A

LDAX

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7
Q

the contents of the designated register pair point to a memory location. this instruction copies the contents of that memory location into the accumulator

A

LDAX

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8
Q

Load register pair immediate

A

LXI

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9
Q

This instruction loads 16-bit data in the register designated in the operand

A

LXI

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10
Q

Load H and L registers direct

A

LHLD

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11
Q

Store accumulator direct

A

STA

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12
Q

Store H and L registers direct

A

SHLD

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13
Q

Exchange H and L with D and E

A

XCHG

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14
Q

Store H and L registers direct

A

SHLD

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15
Q

Copy H and L registers to the stack pointer

A

SPHL

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16
Q

Exchange H and L with top of stack

A

XTHL

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17
Q

Push register pair onto stack

A

PUSH

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18
Q

Pop off stack to register pair

A

POP

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19
Q

Output data from accumulator to a port with 8-bit address

A

OUT

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20
Q

Input data from accumulator to a port with 8-bit address

A

IN

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21
Q

Add register or memory to accumulator

A

ADD

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22
Q

Add register/memory to accumulator with carry

A

ADC

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23
Q

Add immediate to accumulator

A

ADI

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24
Q

Add immediate to accumulator with carry

A

ACI

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25
Q

Add register pair to H and L registers

A

DAD

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26
Q

Subtract register/memory from accumulator

A

SUB

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27
Q

Subtract source and borrow from accumulator

A

SBB

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28
Q

Subtract immediate from accumulator

A

SUI

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29
Q

Subtract immediate from accumulator with borrow

A

SBI

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30
Q

Increment register/memory by 1

A

INR

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31
Q

Increment register pair by 1

A

INX

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32
Q

Decrement register/memory by 1

A

DCR

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33
Q

Decrement register pair by 1

A

DCX

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34
Q

Decimal adjust accumulator

A

DAA

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35
Q

Jump unconditionally

A

JMP

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36
Q

jump on carry

A

JC

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37
Q

Jump on no carry

A

JNC

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38
Q

Jump on positive

A

JP

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39
Q

Jump on minus

A

JM

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40
Q

jump on zero

A

JZ

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41
Q

jump on no zero

A

JNZ

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42
Q

jump on parity even

A

JPE

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43
Q

jump on parity odd

A

JPO

44
Q

unconditional subroutine call

A

CALL

45
Q

call on carry

A

CC

46
Q

call on no carry

A

CNC

47
Q

call on positive

A

CP

48
Q

call on minus

A

CM

49
Q

Call on zero

A

CZ

50
Q

call on no zero

A

CNZ

51
Q

call on parity even

A

CPE

52
Q

call on parity odd

A

CPO

53
Q

Return from subroutine unconditionally

A

RET

54
Q

return on carry

A

RC

55
Q

return on no carry

A

RNC

56
Q

return on positive

A

RP

57
Q

return on minus

A

RM

58
Q

return on zero

A

RZ

59
Q

return on no zero

A

RNZ

60
Q

Return on parity even

A

RPE

61
Q

return on parity odd

A

RPO

62
Q

Load program counter with HL contents

A

PCHL

63
Q

Restart

A

RST

64
Q

compare register/memory with accumulator

A

CMP

65
Q

compare immediate with accumulator

A

CPI

66
Q

logical AND register/memory with accumulator

A

ANA

67
Q

logical AND immediate with accumulator

A

ANI

68
Q

exclusive OR register/memory with accumulator

A

XRA

69
Q

exclusive OR immediate with accumulator

A

XRI

70
Q

logical OR register/memory wityh accumulator

A

ORA

71
Q

Logical OR immediate with accumulator

A

ORI

72
Q

Rotate accumulator left

A

RLC

73
Q

Rotate accumulator right

A

RRC

74
Q

each binary bit of accumulator is rotated left by one position

A

RLC

75
Q

each binary bit of accumulator is rotated right by one position

A

RRC

76
Q

rotate accumulator left through carry

A

RAL

77
Q

rotate accumulator right through carry

A

RAR

78
Q

each binary bit of accumulator is rotated right by one position through the carry flag

A

RAR

79
Q

each binary bit of accumulator is rotated left by one position through the carry flag

A

RAL

80
Q

Complement accumulator

A

CMA

81
Q

complement carry

A

CMC

82
Q

set carry

A

STC

83
Q

No operation

A

NOP

84
Q

halt and enter wait state

A

HLT

85
Q

disable interrupts

A

DI

86
Q

enable interrupts

A

EI

87
Q

Read interrupt mask

A

RIM

88
Q

Set interrupt mask

A

SIM

89
Q

Serial Output Data

A

SOD

90
Q

Serial data enable

A

SDE

91
Q

don’t care

A

XXX

92
Q

Reset RST 7.5

A

R7.5

93
Q

Mask set enable

A

MSE

94
Q

Restart address of instruction RST 0

A

0000H

95
Q

Restart address of instruction RST 1

A

0008H

96
Q

Restart address of instruction RST 2

A

0010H

97
Q

Restart address of instruction RST 3

A

0018H

98
Q

Restart address of instruction RST 4

A

0020H

99
Q

Restart address of instruction RST 5

A

0028H

100
Q

Restart address of instruction RST 6

A

0030H

101
Q

Restart address of instruction RST 7

A

0038H

102
Q

Restart address of interrupt TRAP

A

0024H

103
Q

Restart address of instruction RST 7.5

A

003CH

104
Q

Restart address of instruction RST 5.5

A

002CH

105
Q

Restart address of instruction RST 6.5

A

0034H

Microprocessor (2 decks)

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