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CPSC 2482- Comp Organization > midterm study > Flashcards

midterm study Flashcards

1
Q

the output value, Q, only changes on the rising edge of G

keeps the internal SR latch from going into an invalid state

Is a great circuit to use in a register

A

D-Flip Flop

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2
Q

for an SR latch, what states are valid?

A

10
01
11

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3
Q

The output value, Q, changes with the D input as long as G is high

Keeps the interal SR latch from going into an invalid state

A

D- latch

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4
Q

what logic gate adds two bits together and ignores any carry

A

xor

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5
Q

Using an adder, when is there a carry?

A

both input bits are 1

the sum of the input bit is 1 and the carry in is 1

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6
Q

what binary number represents false?

A

0
zero

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7
Q

what binary number represents true?

A

1
one

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8
Q

_____ Gate: If both the inputs are high then the output is also high

A

AND

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9
Q

_____ Gate: If a minimum of one input is high then the output is High

A

OR

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10
Q

____ Gate: If the minimum one input is high then only the output is high

A

XOR

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11
Q

______ Gate: If the minimum one input is low then the output is high

A

NAND

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12
Q

____ Gate: If both the inputs are low then the output is high.

A

NOR

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13
Q

The Following truth table has what outputs with an AND gate
A B
0 0
0 1
1 0
1 1

A

Output
0
0
0
1

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14
Q

if one of the two inputs of an AND gate is zero (0) then the output will be ____

A

zero

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15
Q

The Following truth table has what outputs with an OR gate
A B
0 0
0 1
1 0
1 1

A

Output:
0
1
1
1

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16
Q

If one of two the inputs to the OR gate is 1 then the output will be _____

A

One

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17
Q

In a NOR gate, the input One (1) creates an output _____ and an input of Zero (0) gives and output of _____

A

Zero
One

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18
Q

The Following truth table has what outputs with an NAND gate
A B
0 0
0 1
1 0
1 1

A

Output
1
1
1
0

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19
Q

The _____ gate is a digital logic gate with ‘n’ i/ps and one o/p, that performs the operation of the AND gate followed by the operation of the NOT gate.

A

NAND

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20
Q

If one or both of two inputs to the NAND gate is zero (0) then the output will be _____

A

One

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21
Q

The _____ gate is a digital logic gate with n inputs and one output, that performs the operation of the OR gate followed by the NOT gate.

A

NOR

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22
Q

If the inputs are both one’s then the output is 0 and if the inputs are both zero’s then the output is One other wise if a single input is one then the output is zero for what gate?

A

NOR gate

23
Q

The Following truth table has what outputs with an XOR gate
A B
0 0
0 1
1 0
1 1

A

0
1
1
0

24
Q

The _____ gate is a digital logic gate with two inputs and one output. The short form of this gate is Ex-OR. It performs based on the operation of the OR gate. . If any one of the inputs of this gate is high, then the output of the EX-OR gate will be high.

A

XOR

25
Q

If the inputs are both one’s then the output is zero and if the inputs are both zero’s then the output is zero, other wise if a single input is one then the output is One for what gate?

A

XOR gate

26
Q

Carry Look Ahead
Input:
a b c

Sum:
s = ______________

Propagate:
p = ______________

Generate Signal:
g = _________________

A

s = a ⊕ b ⊕ c

p = a + b

g = ab

27
Q

Carry Look ahead:
- there is no ____ ____

  • singal p and g do NOT depend on ___
A

carry out
c

28
Q

Ripple Adder:
Cin of a bit comes from the C of the ____ ____

Daisy chain multiple Full Adders

A

lower bit

29
Q

What two things cause a carry?

A

x =1 && y=1 ← generation (g)

(x =1 || y=1) && Cin ← propagation (p)

30
Q

carry look ahead formula

A

g = xy
p = x xor y

31
Q

there is a carry to a higher bit if:

A

Carry generated by current bit (g=1)

OR There is a carry from the lower bit AND the current bit can propagate it

Formula: C = g + pCin

32
Q

Carry look ahead 3 outputs:

A

g = xy
p = x⊕y
S = x⊕y⊕Cin
Note: p and g do not depend on Cin!!

33
Q

Constructed using a circuit attached to an adder

A

Subtracting is simply adding a 2’s complement

To get 2’s complement:

Complement each bit

Add one to the right most bit.

34
Q

Subtracter boolean equation

A

X-Y == X+(-Y)

mplementing negation:
XOR with 1 negates
Add 1 by making Cin on the adder 1 when XORing 1

35
Q

associative property

A

A ∧ (B ∧ C) = (A ∧ B) ∧ C
A ∨ (B ∨ C) = (A ∨ B) ∨ C

36
Q

Commutative property

A

A ∧ B = B ∧ A
A ∨ B = B ∨ A
A ∨ (B ∧ C) = (A ∨ B) ∧ C
A ∧ (B ∨ C) = A ∧ (B ∨ C)
A ∧ B ∧ C = C ∧ B ∧ A

37
Q

Distributive property

A

A ∨ (B ∧ C) = (A ∨ B) ∧ (A ∨ C)
A ∧ (B ∨ C) = (A ∧ B) ∨ (A ∧ C)

38
Q

Identity law

A

A ∧ True = A
B ∨ False = B

39
Q

Complement law

A

A ∨ A’ = True
B ∧ B’ = False

40
Q

Idempotent law

A

A ∨ A = A
B ∧ B = B

41
Q

double negation law

A

(A’)’ = A
((A ∧ B)’)’ = A ∧ B (same for ∨)
(A ∨ B’)’ ≠ A ∨ B

42
Q

de Morgan’s Law

A

(A ∧ B)’ = A’ ∨ B’
(A ∨ B)’ = A’ ∧ B’

43
Q

Absorptive law

A

A ∧ (A ∨ B) = A
A ∨ (A ∧ B) = A

44
Q

Which logic gate essentially adds two bits together, albeit ignoring any carry.

A

XOR

45
Q

Using an adder, when is there a carry?

A

Both input bits are 1

The sum of the input bits is 1 and the carry in is 1

46
Q

How is the decoder like the multiplexer. How is it different? Both at the circuit level, and in the logic behind them

A

Both the decoder and the multiplexer are used to control signals. AND gates make up the inner circuits of both the decoder and multiplexer. Multiplexers often have an OR gate to output its results. There can be multiple inputs for both decoders and multiplexers, but multiplexers normally selects a singular input and decoders have a single true output line through conversion. Multiplexers are often in the form of 8:1 or 16:1 while decoders are in the form of 2:4 or 4:16. The decoder is a logic circuit with the intention of outputting 2^n lines, while the multiplexer is intended to be a selector.

47
Q

P
A
Ozzy
Is
My
Dads
Detective

A

Level 5- Problem-Oriented
Level 4- Assembly
Level 3- Operating System
Level 2- Instruction
Level 1- Machine
Level 0- Digital logic
Level -1- Device

48
Q

negative
milli
micros
not
pushy
for
a
zoo
yack

A

milli
micro
nano
pico
femto
atto
zepto
yocto

49
Q

positive
kara
mara
got
to
park
e-
z
yeezy

A

kilo
mega
giga
tera
peta
exa
zetta
yotta

50
Q

(D3 S1 S0) + (D2 S1 ~S0) + (D1 ~S1 S0) + (D0 ~S1 ~s0)

A

Multiplexer

51
Q

Q3 = S1 S0 E
Q2 = S1 ~S0 E
Q1 = ~S1 S0 E
Q0 = ~S1 ~S0 E

A

Decoder

52
Q

Half Adder
g = __ ___
p = ___ ____ ___
S = ____ ____ ____ ___ ____

A

X Y
X xor Y
X cor Y xor CIN

53
Q

full adders attached by cin and cout

A

ripple adder

54
Q

Look Ahead adder
S = ___ ___ __ __ __
C = ( ____ ( __ __ ___) __ ___ ___

A

A xor B xor CIN
CIN A xor B + A B

CPSC 2482- Comp Organization (7 decks)

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