MEMORY + I/O Flashcards
RTL?
-fetch-decode-execute MICRO INSTRUCTIONS in RTL
RTL:Fetch
PC has to be implemented.
FUll add-
Fetch-
PC current instruction loaded in MAR
then moved to MBR
MBR goes to IR
and program counter increments from PC to PC+1
Decode
MAR→ X
Content will be brought into
MBR
and then moved to AC
MARIE addresses
Address= each byte has its own address- byte-addressable
In MARIE, it is word-addressable as it stores 2 bytes(i.e 16 bits)
RAM
RAM has multiple chips. can count how many chips in each row and column - 64 chips. NEED TO address each chip as well.
lx w = number of locations and number of bits each chips
64 x 2^14
RAM- 8 columns and 8 columns = 2^11 bytes.
3 bytes 3 bytes R,C and 11 bytes for addressing
2^11 bits, if 4 *4 row col row regardless always 2^11 addresses
Indirect addressing
Implement using Multiplexers-
Indirect Addressing-
Usually
Store X- value of AC to address
Load X- address to AC (opposite of store)
Add X- add X value to AC
Jump X- jump to a particular address
Not very flexible as contents keep changing.
Indirect Addressing-
use address stored at X
Load X- load value(66) stored at address X into AC
LoadI X- look value(66) stored at address X and USE IT AS AN ADDRESS, so now load value(70) from address Y i.e 66 into AC.
- Advantages- addresses dont need to be hard-code in a program.
- can loop with indirect addressing.
000 AC<0
400 AC=0
800 AC>0
Other Indirect Addressing
- Add X- adds value at particular address of X into AC
- AddI X- go to address X→value of address as new address → value of that new address ‘Y’ is addedd in AC
- JumpI X- subroutine useful
- jumps to value of address X and and takes value of new address Y
Subroutine ?
Subroutines- well-defined functions for programs
Main program calls subroutine
E.g Addition X val, Y val, X+Y as Sum
Store return address
JumpI
JnS
JumpI both for subroutines-
returns to caller.
Subroutines in Machine Code→
JnS X- Jump and Store, Stores value of PC into X,jumps then increments and jumps to X+1
Jump to address stored at X
Returns to the calling code.
Program-
…..
Jns X stores the return address at address X.
increments PC to x+1
then JumpI X. last statement takes value of Rx in x and returns back to Rx (return address).
Also classed as I/O:
Storage(hard disks, SSDS, SD Cards)
Networks(WiFi, 4G, Ethernet)
Early vs Now I/O
Early Input output were teletype tapes→binary data very limited I/O. Punched paper tape.
Modern I/O- much more complex, keyboard, mousepads, GPS, printer,s touch screens
Modern I/O Interfaces usually connected through interface-
ethernet, iEEE, PCIe, HDMI, USB
can be internal or external
Why I/O CPU should be wlel connected
I/O and the CPU
needs to be well connected so that
- CPU receive data from I/O device
- CPU Send data to an I/O device
Why send to input devices?
Why receive from output devices?
SEND
-set sensitivity, calibrate, switch on/ off which port numbers.
RECEIVE
-CPU needs to monitor if data has been transmitted ,
check if ready
I/O Devices have their owns registers
e.g keyboard devices- registers(like a buffer) holds currently pressed key.
how to access these machine code registers?
Two methods-
- memory- mapped
- instruction- based I/O
1. Memory mapped
Each I/O register is “mapped” to a special memory address.
Address holds current key pressed of keyboard.
Advantages- no need new instructions, load store
simple
Disadvantages- cant used “mapped” addresses for memory anymore hard to hardcode
a lot of addresses are unavaivalble.
BUGGED programs can accidentally access same address of I/O
- Instruction Based I/O
- Add special instruction to CPU ISA. E.g-Input and Output
- Each I/O register still has an address. separate for I/O
- but addresses are separate from memory.
When to perform I/O?HOW do the CPUs communicate?
TWO METHODS- Programmed and Interrupt-Based I/O
- Programmed- also known as Polling
periodically checking , e.g CPU constantly checking from mouse driver and detection. it checks regardless.
help those devicss that needs to be constantly checked
adv-simple, dont need extra hardware
program can decide how often to poll
disadv- programmer must be carefull(dont poll too much)
CPU always in a loop- power use
- Interrupt- Based I/O
Majority of hardware using IRQs- getting attention of CPU
CPU is notified when it should communicate with I/O device, USB, soundcard.
IRQ needs to be configured.
CPU interrupts current program, then
executes special interrupt (signal to processor- has hardware or software) handler code → can say high priority , low perioriy or medium has hardware or software
and then continues program
Interrupt
Device notifies CPU, CPU interrupted, checks fetch-decode cycle of interrupt handler, sees the RTL.
similar to subroutine jumping
JnS to interrupt handler subroutine, JumpI returns back to CPU program
Interrupt Handler-
must leave CPU same state as before the interrupt.
after IRQ needed to switch from program to IRQ. need to maintain state of the program.
Context switching. CPU maintains the previous program..
Shadow registers-
CPU switches to a separate register called SHADOW REGISTERS
In programming, the interrupt handler saves the registers to memory.
CPU time slicing every program.
Interrupt modern
Interrupt Vector-
memory location of interrupt handler.
how can interrupt handlers differentiate the devices ?
each device has a different interrupt vector and assigned an identification number, to jump to the subroutine(e.g USB subroutine, keyboard handlers, sound handler)
Interrupts in x86 PCS
before had only 15 IRQs
Modern interrupts- many more. Advanced Programmable interrrupt controllers. (APICs)
Adv- fast and tricky
Disadvantages- Interrupt-Based I/O
different devices have diff priorities- keyboard, graphics card
all memory transfer go through the CPU-
read byte from memory , transfer to graphics card
I/O devices are fully controlled by CPU
