Logic Optimization Flashcards
What is gate-level minimization?
The task of designing a digital circuit that is optimal by using the most simplified Boolean expression
The complexity of a digital circuit depends on
The complexity of the corresponding algebraic equation
SOP and POS has how many levels of logic circuit?
2
In this equation what is the terms?
AB+AC+BC / ABC+BCD
AB, AC, BC, ABC, BCD
Which has more terms? the left of right side
AB+AC+BC / ABC+BCD
left side
Which one is the literal?
AB+AC+BC / ABC+BCD
A, B, C, D
Which one has more literals?
AB/ABC
ABC
How do find the best solution/ simplified version
By comparing the simplified version of both POS and SOP forms
What are the logic minimization methods?
Algebraic approach and Karnaugh map
What is the max number of variable for Karnaugh Map?
7, it is a pictorial form of Karnaugh map
What is CMOS technology?
Complementary metal oxide semiconductor
Naturally produces the inverse of the desired logic function, so NAND-NAND implementation will be found often
What is an implicant?
A product term that if true implies that the function is true
What is a prime implicant?
An implicant that cannot be simplified further/ larger using fewer literals. Not unique can be represented in different forms.
What is an essential prime implicant?
A prime implicant that is unique cannot be represented in another way
What method can we use to do logic minimization when a value of a certain function is unspecified
Don’t care conditions
How to find the minimum POS form
We do grouping on the 0’s in the graph then negate them and form their negated version in POS form
A set of logic operations is said to be complete if
any Boolean function can be expressed by in terms of these operations, and it can represent all basic logic operation (AND, OR,NOT)
What are the universal logic gates?
NAND NOR
The output of an odd function is 1 iff
There is an odd number of input variables that equal to 1
Sharing gates between multiple functions may increase cost. True or false
False
What is Multi-output circuit optimization?
A method to optimize the overall circuit by sharing the non-prime implicants.
