Logic Gates Flashcards
What are the three most basic logical operations?
AND, OR, NOT
What is the output of an AND operation for inputs 1 and 0?
0
What is the output of an OR operation for inputs 0 and 1?
1
What is the output of a NOT operation for input 0?
1
Fill in the blank: A truth table of a Boolean function lists the output values for every possible _______.
input value combination
What does a combinational logic function output if more inputs are 1 than 0?
1
What is the alternative symbol for the AND logic function?
∧ or &
What is the alternative symbol for the OR logic function?
∨ or |
What is the alternative symbol for the NOT logic function?
¬ or ‘ or ! or ~
What defines Boolean algebra?
Algebra over two elements: 0 and 1
What are the two binary operations in Boolean algebra?
+ and ∙
What is the result of 1’ in Boolean algebra?
0
What is the result of 0’ in Boolean algebra?
1
Who is the inventor of Boolean logic?
George Boole
What is the priority order of Boolean operators from high to low?
Parentheses, NOT, AND, OR
What does the duality principle state?
The dual of any true statement is also a true statement
What is the commutative law in Boolean algebra?
x ∙ y = y ∙ x and x + y = y + x
What does DeMorgan’s Theorem state for (x ∙ y)’?
x’ + y’
What does the absorption law state for x ∙ (x + y)?
x
What is the result of x ∙ x’?
0
What is the result of x + x’?
1
What is the output of a NAND gate for inputs 1 and 1?
0
What is the output of a NOR gate for inputs 0 and 0?
1
Fill in the blank: Boolean functions can often be expressed in _______ forms.
canonical
What is the result of 1 + x in Boolean algebra?
1
What is the result of 0 ∙ x in Boolean algebra?
0
What is the associative law in Boolean algebra?
x ∙ (y ∙ z) = (x ∙ y) ∙ z and x + (y + z) = (x + y) + z
True or False: Two Boolean expressions may specify the same function.
True
What is the output of an OR operation for inputs 1 and 0?
1
What does the annihilation law state for 0 ∙ x?
0
What is the output of an AND operation for inputs 0 and 0?
0
What is a truth table used for in Boolean functions?
To list output values for every possible input combination
What is the result of the expression x ∙ (y + z)?
x ∙ y + x ∙ z
What is the result of (x + y)’?
x’ ∙ y’
What are some applications of Boolean algebra?
Set theory, mathematical logic, digital system design
What is a minterm?
An AND term consisting of all the variables in their normal form or complement form
For two binary variables x and y, the minterms are xy, xy’, x’y, x’y’.
What is a maxterm?
An OR term consisting of all the variables in their normal form or complement form
Also called standard sums.
What is the number of minterms for n variables?
2^n
This indicates the possible combinations of the variables.
What is the Absorption Property in Boolean algebra?
x ∨ (x ∧ y) = x
What is the Idempotence Law in Boolean algebra?
x = x ∨ x
What is the Sum of Minterms Form?
A Boolean function expressed as a sum of minterms that produce output 1
Example: f1 = x’y’z + xy’z’ + xyz = m1 + m4 + m7.
What is the Product of Maxterms Form?
The complement of a function expressed as a product of maxterms that produce output 0 for the original function
Example: If f = m1 + m4 + m7, then f’ = m0 + m2 + m3 + m5 + m6.
What are Canonical forms in Boolean algebra?
Forms that can be expressed as a sum of minterms or a product of maxterms.
What is DeMorgan’s theorem?
It provides a way to express the complement of a function in terms of its minterms and maxterms.
What is the difference between Sum-of-Products (SOP) and Product-of-Sums (POS)?
SOP form is a sum of products of literals; POS form is a product of sums of literals.
What does a module in Verilog represent?
A basic unit of design in hardware description language (HDL)
It contains declarations for inputs, outputs, and internal signals.
What does the assign statement do in Verilog?
It creates a continuous assignment to a wire signal.
What is the output of a three-input majority function in Verilog?
It outputs true when at least two of the three inputs are true.
Fill in the blank: A logical function can be represented by a _______.
logic diagram (schematic)
What is the significance of the wire type in Verilog?
It represents a signal type that is continuously driven by an assign statement or connected to a module output.
What does the always block do in Verilog?
It allows for the evaluation of conditions whenever the specified signals change.
True or False: The SOP/POS form of a function is unique.
False
What is the purpose of a testbench in Verilog?
To simulate the behavior of the design and verify its functionality.
What does the case statement do in Verilog?
It allows for multiple conditions to be checked and corresponding outputs to be assigned.
What is a Hardware Description Language (HDL)?
A language used to describe the structure and behavior of electronic circuits.
Fill in the blank: The output of a majority function is true when _______.
at least two of the three inputs are true.
What does the term ‘combinational logic’ refer to in Verilog?
Logic where the output depends only on the current inputs.
What is an always block in Verilog?
An always block is a continuous procedural block that gets triggered each time a signal in its sensitivity list changes.
What does the case statement do in Verilog?
The case statement selects values based on the expression provided, allowing for multiple conditions to be evaluated.
What does the default case cover in a Verilog case statement?
The default case covers values not listed in the case statement.
What is one characteristic of combinational modules in Verilog?
Combinational modules use only assign statements, case or casex statements, if-else statements within an always block.
What should be avoided in Verilog combinational modules?
Do not use loops.
What is the guideline for naming signals in Verilog?
Use meaningful signal names, such as tempHigh instead of th.
What is the recommended length for leaf modules in Verilog?
Leaf modules should not be more than 40 lines.
What is the importance of comments in Verilog code?
to clarify the code.
What should activation lists for case statements include?
Activation lists should include ALL inputs or use ‘*’.
When should constants be defined in Verilog?
All constants should be defined if used more than once.
How should buses (multi-bit signals) be numbered?
Buses should be numbered high to low.
What is the preferred signal state for all signals in Verilog?
All signals should be high-true, except primary inputs and outputs.
What should you do if you can’t visualize the logic your Verilog will generate?
If you can’t visualize it, the result will not be pretty.
What is Boolean algebra used for?
Boolean algebra is used to manipulate logic equations.
What does Verilog describe?
Verilog describes hardware for simulation and synthesis.
Fill in the blank: Logic diagrams represent _______.
[logic equations]
True or False: Logic gates can be represented in Verilog.
True
Mention Identity Axiom
1.X=X, 0+X=X
Mention Annihilation Axiom
1+X=1, 0.X=0
Mention Associative Theorem
X(YZ)=(XY)Z, (X+Y)+Z=X+(Y+Z)
Mention Distributive Law
X(Y+Z)=XY+XZ, X+(YZ)=(X+Y).(X+Z)
What theorem is this?
X.X=X
X+X=X
Idempotence
What Theorem is this?
X.X’=0
X+X’=1
Complementation
Mention Absorption Theorem
X(X+Y)=X, X+(XY)=X
What Theorem is this?
XY+XY’= X
(X+Y)(X+Y’)=X
Combining
Mention the De Morgan’s Theorem
(XY)’= (X+Y)’
(X’+Y’)=X’Y’
What Theorem is this?
(X’)’=X
Involution
What Theorem is this?
(XY) + (X’Z)+(YZ)=XY+X’Z
(X+Y)(X’+Z)(Y+Z)=(X+Y)(X’+Z)
Consensus
To prove a Boolean equation we can use? The method is called?
Case or Truth table, Perfect Induction
Give me the equation for Exclusive OR (XOR)
X’Y+XY’
Give me the equation for The negated version of XOR
XY+X’Y’
What other gates do we have other than AND, OR, & NOT
NOR, NAND, XOR
