Logic Flashcards
NOT Gate (Inverter) specs
- Output is opposite the input
OR Gate specs
- Any high gives a high
AND Gate specs
Any low gives a low
NOR Gate specs
Any high gives a low
NAND Gate specs
Any low gives a high
XOR Gate specs
Any high gives a high but not both
XNOR Gate secs
Any high gives a low but not both
What does Boolean Algebra define?
Logic (AND, OR, NOT etc.) applied to anything that has only 2 states
Logic (and computers) can also be accomplished _____ (DNA. neurons) or _____ or _____.
Organically
Optically
Chemically
Complex problem involving many logic functions can be greatly simplified by applying?
Boolean Laws
Idempotent rule (Redundancy rule)
AA = A A + A= A A1 = A A0 = A A + 1 = 1 A + 0 = A
Law of Complementation
A(not A) = 0
A + (not A) = 1
(not not A) = A
Demorgans Laws
AKA Alternate Logic
- To “demorganize” or determine the alternate logic for a gate:
1) Invert the inputs
2) Change the gate (or sign)
3) Invert the output
Demorganization can only be applied to 2 levels of logic?
- a product of sums
- a sum of products
Another method to Demorganize is to “________________”
Break the line and change the sign
You can not break more than one line at a time but you can break one line more than once in a single step
Commutative Law
AB = BA A+B = B+A
Distributed Law
A(B+C) = AB + AC
Associative Law
A(BC) = C(AB)
Laws of Absorption
A(A + B) = A
A + (AB) = A
Human to machine =
Encoding
Machine to human =
Decoding
Human encoding forms
Numbers, letter, symbols
Video
Audio
Machine decoding forms
Binary Octal Hex BCD ASCII
Flip flops are used as ______ devices?
Memory
What are the 4 types of FFs?
- SR NOR and NAND
- Clocked RS
- D type
- JK
SR NOR and NAND are both what type of FF?
Asynchronous
SR NOR FF specs
- Active High
- Q is set with a 1 on S
- Q is reset with a 1 on R
- 00 is the memory/no change state
- 11 is the prohibited/illegal state
SR NAND FF specs
- Active Low
- Q is set to a 1 with a 0 on S
- Q is reset to a 0 with a 0 on R
- 11 is Memory function
- 00 is prohibited function
Clocked RS FF specs
- Synchronous
- When there is a 0 on CLK the outputs are frozen
- 1 on CLK and 0 on RS is memory state
- 111 is prohibited state
- Set with a 1 on CLK and S
- Reset with a 1 on CLK and R
JK FF does not have prohibited state, instead at 11 it is?
Toggle state
For JK FF, Q output is ____ the clock frequency?
1/2
What are the asynchronous parts of a JK FF?
PRS and CLR
PRS and CLR are active ____?
Low
0 on PRS Q =
1
0 on CLR Q =
0
A 1 on both PRS and CLR is?
Toggle mode for JK
What is the most popular gate to use to make all other gates?
NAND
also least power consumption
A modulus 16 counter counts from ___ to ____
A modulus 10 counter counts from ___ to ____
0-15
0-9
For an up counter, use the ____ function and the ___ output
CLR
Q
For a down counter use the ____ function and the __ output?
PRS
Not Q
What is a shift register?
A chain of FFs used to move binary data from one location to another
ex. calculator display is a shift left register
Serial Loading
- Data is entered 1 BIT at a time
- An 8 BIT BYTE requires 8 clock pulses
Parallel Loading
- Data is moved simultaneously with one pulse
Serial Out
- Data is shifted out 1 BIT at a time
Parallel Out
Data is shifted out all at once
Simplifying circuits should always be done to?
- Reduce cost
- Power consumption
- Space
- Time
Another name for flip flop?
Latch
Astable multivibrator =
Oscillator
Monostable multivibrator =
One shot
Bistable multivibrator =
Flip flop AKA Latch
FFs build basic building blocks for what types of circuits?
Counters and Memory
Shift Registers
Which FF has no invalid state?
JK
Which FF is the most widely used?
JK
On a timing or waveform diagram the horizontal distance stands for _____ and the vertical distance stands for ____?
Time
Volts
The FF is a basic digital circuit with a _____ characteristic that can be used to store info.
Memory
The FF circuit is also called a?
Bistable multivibrator
The outputs are always _____ logic levels
Binary
What makes a FF synchronous?
A clock input
The clocked FF is normally in the sync or async mode?
Sync
FF are wired together to form?
Counters
Registers
Name one application of the simple RS FF?
Bistable multivibrator
Switch debouncer
What do shift registers do in a simple calculator?
Store temporary data
What are the 2 common classifications of shift registers?
Serial
Parallel
Advantages and disadvantages of serial?
Slower but simple and less wiring
Advantages and disadvantages of parallel
Faster, more wiring, more complex
On a logic probe the green LED =
logic 0
On a logic probe the red LED =
Logic 1
The basic 555 configuration is used for?
Multivibrators
ex. clocks, timers etc.
2 main types of logic gate families?
- CMOS (Complimentary Metal Oxide Semi Cons)
2. TTL (Transistor Transistor Logic)
CMOS specs
- FET type transistors
- High efficiency
- Achieved using insulated gates
- Voltage supply 3V to 18V
Precautions to take when handling CMOS devices?
- Grounding straps with wrist bands
- Grounded mats on our work benches
- Static rated packaging
TTL specs
- Use BJT transistors
- More robust but not as efficient
- Voltage supply 5V + or - 0.25V
IC Pin Out =
How the gates are connected to the pins of the IC
IC Fan Out =
The number of gates that an output can drive
Operational amps are a relatively ___ power amp
Low (about 1/2W)
Op Amps are used as ?
Building blocks for industrial processes
- comparators
- integrators
- differentiators
For op amps the Gain, input Z, output Z, bandwidth are dependent on?
The external components we connect
2 types of op amp inputs?
Inverting
Non-inverting
The output of an op amp is _______ times the difference between the inputs?
200,000
Inverting amp formula
Gain = Rf/Rin Vout = -Vin(Rf/Rin)
Voltage follower op amp specs
Buffer
Gain = 1 (unity)
Used to isolate circuits
Non inverting amp formula
Gain = A = Rf/Rin + 1
Summing Amp formulas
Vout = - (V1 Rf/R1 + V2 Rf/R2 + V3 Rf/R3)
Summing amp if R1 = R2 = R3 = Rf then the voltages will be ?
Added together
Summing amp is R1 = R2 = R3 = 3 x Rf then the voltages will be?
Averaged
Integrator amp, Vout varies?
How long the input has been applied
Differentiator amp, Vout varies?
With how quickly the input is changing
An integrator op amp is essentially a?
low pass filter
Integrator op amp has more output if frequency is?
Lower
Integrator Vout formula?
Vout = -Vin x 1/RC x T
Integrator output is proportional to the?
Product of the amplitude and duration of the input signal (area under the curve)
Integrator op amp suffers from?
Drift , any DC offset voltage will cause the integrator to drift and eventually saturate
What is placed in parallel with the capacitor in a integrator op amp to reduce drift?
A high value resistor
A differentiator op amp responds to ?
rate of change of the input signal
A differentiator op amp is essentially a ?
High pass filter
for a differentiator op amp more output if frequency is?
Higher
differentiator op amp instantaneous output is proportional to?
Instantaneous rate of change at its input
differentiator op amp Vout formula?
Vout = -RC x (change in Vin/ change in time)
differentiator op amp suffers from?
High frequency noise gain
What will limit the high frequency noise gain on a differentiator op amp?
A resistor in series with the input capacitor
What kind of transistor are used in the TTL family of logic ICs?
BJTs (bipolar junction)
What kind of transistor are used in the CMOS family of logic gate ICs?
FET (mosfets)
Traditionally which of the two families of ICs has had the lowest power dissipation rating?
CMOS
Which of the two families has had the lower propagation delay?
TTL
The TTL family come in the ____ series. The military uses the ____ series?
7400
5400
The operating voltage of TTL ICs is?
5V +/- 0.25V
What is meant by the term noise margin as applied to logic gates?
Difference between valid input and output for highs and for lows
In general which family of ICs has the largest fan-out?
CMOS (50)
The CMOS family of ICs uses the _____ series and the ___ series?
4000A and 4000B
A typical fan-out for a standard TTL IC is about ____ and a CMOS is about ____?
10
50
The minimum output high of a TTL gate is?
2.4V
The minimum input high of a TTL gate is?
2.0V
The max output low of a TTL gate is?
0.4V
The max input low of a TTL gate is?
0.8V
Which logic gate family is most susceptible to damage from static electricity?
CMOS
Which logic gate is family is most likely to have errors introduced by noise signals added to the coupling connections?
CMOS
What should be done with an unused input to an OR gate?
Tied low
What else could you do with the unused OR gate input if you were not concerned with a fan out of a preceding gate?
Tied to another unit
What should be done with an unused input to an AND gate?
Tied high
