Lesson 4a

Question 1

What is dance hall arch

Answer 1

CPUS on one side of integrated network. Memory on the other side

Question 2

What is smp

Answer 2

symmetric multiprocessor. All cpus share the same memory

Question 3

In dance ahll and smp how many caches exist

Answer 3

Once Cache per cpu

Question 4

what is DSm

Answer 4

Distributed shared memory

Question 5

How is smp different from dsm

Answer 5

Each cpu has its own memory in dsm. in smp we have a single memory

Question 6

How many network connections (dance hall?)

Answer 6

One all cpus are connected to it

Question 7

What is the process for getting memory using smp

Answer 7

each cpu checks its local cache before going to the system bus and then main memory

Question 8

what is cache coherence problem

Answer 8

when a value y is cached across all cpu caches and one cpu updates the value. How are the other caches invalidated and updated?

Question 9

What is the memory consistency model

Answer 9

A contract between the software and hardware that specifies how the data stay consistent across caches and also when multiple processors are accessing the same memory locations

Question 10

What is the sequential consistency model (SC)

Answer 10

Program order arbitrary interleaving (think of card shuffle) (Lessly Lamport)

Question 11

Program Order?

Answer 11

Memory instructions are performed in the order written. Linearly executed one after the other.

Question 12

Arbitrary Interleaving

Answer 12

When P1 and P2 access memory it is arbitrary

Question 13

what question does memory consistency answer?

Answer 13

What is the model presented to the programmer

Question 14

What question does cache coherence answer

Answer 14

How is the system implementing the model in the presence of private caches?

Question 15

What is NCC

Answer 15

Non-cache coherence has shared memory and private caches but when memory is changed it is a software problem to keep it in sync

Question 16

What is CC processor

Answer 16

Cache Coherent. It is enforced (insured) by the hardware

Question 17

Hardware CC what happens when a value is updated?

Answer 17

An “invalidate” message is sent on the bus and the other cpu caches are cleared (invalidated) of this entry.

Question 18

What is a write update in hardware CC?

Answer 18

Instead of invalidating the cache, each cache is updated with the new value (“if they have an entry”)

Question 19

What are the scalability pros and cons of SMP

Answer 19

Pro: Parallelism increases processing power
Con: Increased overhead due to CC

Question 20

Is the performance increase linear with the number of processors introduced

Answer 20

No, it is the “actual”performance which is between the expected performance and the introduced overhead

Question 21

When do shared memory machines scale well?

Answer 21

“When you don’t share memory”