Lesson 2d (L3) Flashcards
why was mach slow
it wanted to be portable
microkernel is what
services such as file system, memory manager, cpu scheduler are set above the kernel
what does the micro-kernel provide for the OS processes to communicate
IPC
What causes performance loss
a lot of boarder crossing. Since services use IPC (PPC protected procedure calls) they have border crossing when talkig to each other 100x slower than normal procedure call
In traditional microkernel are system services in their own address space
yes
what are the services L3 provides
Address space, threads, IPC, UID
In l3 are system services in their own address pace
No, they are in their own protection domain
What is l3 argument about efficency
It is about the implementation not the structure of a microkernel
Historic strikes against micro kernels
- border crossing cost, 2. address space switches, thread switches and IPC for PPC 4. Memory effects (locality loss code cache)
What are PPC
protected procedure calls
Does intel x86 have a address space tlb?
no
How is the intel tlb dvided
kernel address space and user address space
what does the address tlb contain in addition to tag and index
the PID of the process
How did l3 implement protection when cpu does not provide address tlb
segment registers
what are segment registers used for in l3
base and bound memory regions for os services. Protected memory areas
How many cycles does a border crossing tak in l3
123
How does l3 compare to a hand coded implementation of a border crossing
about the same equivalent
how man cycles does mach take for border crossing on same hardware
900
why did spin and exokernel decry micro-kernels
they used mach’s border crossing cycle count for comparison
why are border crossing slower in mach
they designed for portability
do you always have to flush tlb on context switch
Not if it is a address space tagged TLB (MIPS has this)
when do segment work well for the l3 kernel
When the protection domain that they represent is small
what has to happen on a large protection domain during a context switch
The tlb needs to be flushed if the tlb is not as tagged
what is an as tagged tlb
address psace tagged. A pid is added to the tlb and that is verified during address translation
what has a higher cost in terms of performance tlb flush or loss of locality
locality. Since the cache will be cold
what are the explicit cost of context switch
tlb flush
implicit cost of context switch
loss of locality
most important question about address space switching
large or small protection domain
how did l3 debunk address space switching cost myth
showed address switch cost are minimal if designed well and that cache misses cost more
how was the myth about thread switching debunked
by showing that by construction the switching time could match exokernel, spin and monolithic
memory effect debunked
pack things in such a way that the protection domain stays small and the cache stays warm
Why was mach border crossing so slow
the focus on portability lead to code bloat, larger mem footprint -> less locality -> cache misses
What is the l3 thesis in regards to OS construction
using the right set of micro-kernel abstractions and processor-specific implementation of the kernel.
