Lesson 2d (L3)

Question 1

why was mach slow

Answer 1

it wanted to be portable

Question 2

microkernel is what

Answer 2

services such as file system, memory manager, cpu scheduler are set above the kernel

Question 3

what does the micro-kernel provide for the OS processes to communicate

Answer 3

IPC

Question 4

What causes performance loss

Answer 4

a lot of boarder crossing. Since services use IPC (PPC protected procedure calls) they have border crossing when talkig to each other 100x slower than normal procedure call

Question 5

In traditional microkernel are system services in their own address space

Answer 5

yes

Question 6

what are the services L3 provides

Answer 6

Address space, threads, IPC, UID

Question 7

In l3 are system services in their own address pace

Answer 7

No, they are in their own protection domain

Question 8

What is l3 argument about efficency

Answer 8

It is about the implementation not the structure of a microkernel

Question 9

Historic strikes against micro kernels

Answer 9

1. border crossing cost, 2. address space switches, thread switches and IPC for PPC 4. Memory effects (locality loss code cache)

Question 10

What are PPC

Answer 10

protected procedure calls

Question 11

Does intel x86 have a address space tlb?

Answer 11

no

Question 12

How is the intel tlb dvided

Answer 12

kernel address space and user address space

Question 13

what does the address tlb contain in addition to tag and index

Answer 13

the PID of the process

Question 14

How did l3 implement protection when cpu does not provide address tlb

Answer 14

segment registers

Question 15

what are segment registers used for in l3

Answer 15

base and bound memory regions for os services. Protected memory areas

Question 16

How many cycles does a border crossing tak in l3

Answer 16

123

Question 17

How does l3 compare to a hand coded implementation of a border crossing

Answer 17

about the same equivalent

Question 18

how man cycles does mach take for border crossing on same hardware

Answer 18

900

Question 19

why did spin and exokernel decry micro-kernels

Answer 19

they used mach’s border crossing cycle count for comparison

Question 20

why are border crossing slower in mach

Answer 20

they designed for portability

Question 21

do you always have to flush tlb on context switch

Answer 21

Not if it is a address space tagged TLB (MIPS has this)

Question 22

when do segment work well for the l3 kernel

Answer 22

When the protection domain that they represent is small

Question 23

what has to happen on a large protection domain during a context switch

Answer 23

The tlb needs to be flushed if the tlb is not as tagged

Question 24

what is an as tagged tlb

Answer 24

address psace tagged. A pid is added to the tlb and that is verified during address translation

Question 25

what has a higher cost in terms of performance tlb flush or loss of locality

Answer 25

locality. Since the cache will be cold

Question 26

what are the explicit cost of context switch

Answer 26

tlb flush

Question 27

implicit cost of context switch

Answer 27

loss of locality

Question 28

most important question about address space switching

Answer 28

large or small protection domain

Question 29

how did l3 debunk address space switching cost myth

Answer 29

showed address switch cost are minimal if designed well and that cache misses cost more

Question 30

how was the myth about thread switching debunked

Answer 30

by showing that by construction the switching time could match exokernel, spin and monolithic

Question 31

memory effect debunked

Answer 31

pack things in such a way that the protection domain stays small and the cache stays warm

Question 32

Why was mach border crossing so slow

Answer 32

the focus on portability lead to code bloat, larger mem footprint -> less locality -> cache misses

Question 33

What is the l3 thesis in regards to OS construction

Answer 33

using the right set of micro-kernel abstractions and processor-specific implementation of the kernel.