Brainscape's Knowledge GenomeTM

Browse over 1 million classes created by top students, professors, publishers, and experts.


See full index

350 > IO > Flashcards

IO Flashcards

1
Q

what’s a bus?

A

a communication pathway between components of a computer

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
2
Q

what’s a crossbar?

A

connects any input to any output

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
3
Q

what’s a bridge?

A

connects two different buses

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
4
Q

IO APIC is?

A

IO advanced programmable interrupt controller
the part of the processor that handles interrupts from devices

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
5
Q

SRAM

A

static
very fast, used to cache slower memory

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
6
Q

DRAM

A

dyanmic
capacitor + gate to store a bit
very dense, but slower

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
7
Q

VRAM

A

video
dual ported i.e. can write while another component reads

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
8
Q

ways to communicate with a device

A

mmapped device registers
device memory
direct memory access

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
9
Q

mmapped device regs

A

some ranges of physical addresses correspond to device registers
lw/sw gets status/sends instructions to a device, not RAM

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
10
Q

device memory

A

device has memory and OS can write to the device through the IO bus rather than an address
uses special IO instructions in and out

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
11
Q

DMA

A

place instructions to device in RAM
poke device by writing to its registers
device performs action and generates interrupt when done

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
12
Q

disadvantages of polling

A

busy waiting
xor high latency

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
13
Q

receive livelock is

A

CPU spends all its time handling device interrupts because packets arrive too quickly and the interrupt handler has high priority

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
14
Q

what are interrupt driven devices good for?

A

disk requests

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
15
Q

head switch times are comparable to

A

short seek times

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
16
Q

LBA

A

logical block addressing
disk interface presents the disk as a linear array of blocks

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
17
Q

CHS

A

cylinder, head, sector

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
18
Q

zoning

A

more sectors on larger tracks

How well did you know this?
1
Not at all
2
3
4
5
Perfectly
19
Q

track skewing

A

sector 0 position varies by track to improve sequential access times

20
Q

sparing

A

flawed sectors not properly storing data are remapped to locations

21
Q

seek phases

A

speedup
coast
slowdown
settle

22
Q

avg seek

A

max_seek / 3

23
Q

FCFS tradeoffs

A

+ easy impl
+ good fairness
- cannot exploit locality to min seek time
- increases avg latency and decreases throughput

24
Q

SPTF tradeoffs

A

+ exploit locality to min seek time
+ higher throughput
- starvation
- hard to know fastest request

25
Q

idea of aged SPTF

A

give older requests higher priority

26
Q

elevator scheduling (SCAN)

A

sweep across disk, service requests as track is approached

27
Q

SCAN tradeoffs

A

+ takes advantage of locality
+ bounded waiting
- middle tracks serviced more often
- could miss locality SPTF exploits

28
Q

C-SCAN is

A

only sweep in one direction and return to the beginning again

29
Q

VSCAN(r)

A

uses effective positioning time
if request not in same direction of previous seek, Teff = Tpos + r Tmax
penalty for changing directions

30
Q

special values of VSCAN(r)

A

r = 0 gives SPTF
r = 1 gives SCAN
r = 0.2 good in practice

31
Q

interrupt driven devices

A

device interrupts processor when an event happens
handler asks device what happened (data ready, buffer free, request complete)

32
Q

limitations of flash memory

A

limited number of overwrites possible
random writes very expensive
limited durability (charge can wear out over time)

33
Q

flash translation layer

A

FTL provides wear leveling so writing to the same logical block doesn’t wear out a physical block

34
Q

NAND flash

A

used for storage
high density
faster erase/write times
needs error correction

35
Q

NOR flash

A

faster reads in smaller data units
can execute code
much slower erases

36
Q

NAND flash page

A

2112 bytes - 2048 data 64 metadata/error correcting code

37
Q

NAND flash blocks

A

blocks = 64 (SLC) 128 (MLC) pages
blocks divided into 2-4 planes

38
Q

NAND flash planes

A

planes can access their blocks in parallel to overlap latencies

39
Q

NAND flash read/reuse

A

can read one page at a time
must erase a whole block before reusing it

40
Q

SCSI domain consists of

A

devices and an SDS bus connecting the devices

41
Q

devices in SCSI are

A

host adapters (system bus to SCSI bus) and SCSI controllers (bus to device)

42
Q

device roles in SCSI

A

initiator, target
traditionally host adapter initiator and controllers targets

43
Q

SCSI request is

A

a command from initiator to target

44
Q

LUN in SCSI

A

controllers have >= 1 LUN
each LUN maintains a queue of tasks
initiator can link commands, so no intervening tasks i.e. atomic

45
Q

SCSI exceptions/errors

A

after an error, stop executing most commands
prevents unwanted commands from executing
simplifies device impl

46
Q

cost to transfer 1 sector?

A

max_rot_latency/sectors_per_track

350 (6 decks)

Brainscape helps you reach your goals faster, through stronger study habits.
© 2025 Bold Learning Solutions. Terms and Conditions