Interupts/Week5 Flashcards
What is a “process” ?
In operating systems, a process is an instance of running program.
* More formally, process can be viewed as a collection of all system resources used
for executing some program.
What is “multiprocessing” ?
having multiple harts, which are capable of executing multiple streams of
machine instructions simultaneously
What is “multitasking” ?
periodically switching a signle hart between multiple streams of machine
instructions
What is a “process context” ?
process context is the minimal amount of data – usually
contents of some or all processor registers – that must be saved to allow the
process to be interrupted and, later, resumed.
What is a “hart” ?
A pice of hardware within CPU that can fetch and perform instructions is usually called
“processor hardware thread”. It has its own
* Set of registers (x0-x31, …)
* Program counter (pc)
* control circuits that can fetch and pefrom instructions from memory
What happens when a device needs attention and sets its IRQ to 1.
When the CPU detects IRQ equal to 1, it finishes executing the current instruction but
instead of processing the next instruction, it:
1) Sets the bit corresponding to the device in the special Cause register
2) Saves the address of the next instruction in the special Exception Program Counter
(ECP) register
3) Disables all interrupts by resetting the Interrupt Enable (IE) bit in the Status register
4) Jumps to the starting address of the Interrupt Service Routine (ISR)
What is the “Interupt Service Routine” ?
The Interrupt Service Routine:
1) Saves contents of all CPU registers that ISR will use
2) Determines which device caused the interrupt and why (by reading status registers)
3) Services the device (e.g. supplies or consumes device data through MMIO registers)
4) Ensures that CPU sents IACK to the device
5) Restores contents of all CPU registers that ISR used
6) Returns to the interrupted task
What does the “mstatus” register do ?
(Machine Mode Status) This register enables overall interupt processing. Writing a 1 into the least significant bit allows for interupt handling.
What does the “mie” register do ?
(Machine Mode enterupt enable); This register controls interupt processing from specific sources
- writing 0x001 enables software interupts.
-writing 0x10 enables timer interupts.
-writing 0x100 enables external interupts.
What does the “mtvec” register do ?
(Machine Mode Trap Vector); This registers stores the address of the interupt service reoutine also known as the trap handler. When interupt occurs, the CPU jumps to this address to handle the interupt.
What does the “mscratch” register do ?
(Machine Mode Sratchoad Register); This register servers as a holding place for a CPU register value. Its used for temporary storage during the interupt handling.
What does the “mepc” register do ?
(Machine Mode Exception Program Counter); This register contains the program counter value at the time of an interupt. Its used by mret instruction to return from an interupt.
What does the “mcause” register do ?
(Machine Mode Interupt Cause); This register describes the cause of an interupt. It helps identify weather the interupt was due to an external even, a timer, or other reasons.
How does an “interupt” occur?
An interrupt is caused by a device external to a hart (e.g. timer, or MMIO
keyboard)
How does a “Software Exception” occur?
A software exception is caused by the hart itself
━ Arithmetic exception (e.g. division by zero)
━ Attempt to execute an unknown or unsupported CPU instruction
━ Attempt to access non-existent or prohibited memory location
━ User program invoking a system call (environment call)
