Interrupts Flashcards
An interrupt is always a bad thing for a CPU
True False
False
Level-triggered interrupts can be falling or rising edge.
True False
False
A CPU can ____ data onto a stack and later it must ____ it off again
A CPU can PUSH data onto a stack and later it must POP it off again
Inside a microprocessor, a “timer” is:
A built-in clock unit A counter that can run down or up Software that implements a stopwatch function An ISR that is triggered by the RTC
A counter that can run down or up
Why should you only clear the interrupt flag before exiting an ISR?
To prevent the ISR immediately re-running To tidy up the stack before you leave To tell the user that the code has ended Because ISRs cannot use global variables
To prevent the ISR immediately re-running
Interrupts are usually really simple to debug
True False
False
ISR code should ideally be
written with a proper user interface written in a high level language small and efficient only executed at boot time
small and efficient
The watchdog timer (WDT) is designed to restart a system if the software crashes
True False
True
In the lecture, we defined the utilisation for an interrupt as u = (h+c)/T. In general, utilisation is the percentage of time when the processor is busy and h is the timing overhead for handling the interrupt. Suppose the inter-arrival time between two events is 300 cycles and the processor needs 10 cycles for either a pop or a push. For an ISR which requires 15 cycles for completion, what is its utilisation?
T(inter-arrival time between 2 events): 500 cycles
h(timing overhead for handling interrupt): 18 cycles for push + 18 cycles for pop = 36 cycles
c(cycles required by ISR for completion): 20 cycles
u = (h+c)/T = (36 cycles + 20 cycles) / 500 cycles = 56/500 = 0.112
convert to % = 0.112 x 100 = 11.2%
What is the purpose of an interrupt vector table (IVT)?
To hold the address of ISRs which can handle interrupts To store code that prevents interrupts from happening The store the code that causes interrupts to happen To store the ISR code for handling different interrupts
To hold the address of ISRs which can handle interrupts
An RTC crystal or oscillator allows a CPU to:
Connect to peripherals that also have an RTC Provide a signal that can be exactly divided into 1 second Generate its main system clock Improve the timing of its ISRs
Provide a signal that can be exactly divided into 1 second
The primary function of an RTC crystal or oscillator is to provide a highly accurate timekeeping signal that can be divided into precise time intervals, typically 1 second, for tasks such as keeping track of time, date, and scheduling events
The SP is:
a variable that contains data for a short time a register that indicates the end of the stack the "stack push" indicator a stack placeholder the programmer uses to remember where the stack is in memory
a register that indicates the end of the stack
ISR code should ideally be
only executed at boot time written with a proper user interface small and efficient written in a high level language
small and efficient
What is a low level and high level trigger interrupt?
Low-Level Triggered Interrupt: In a low-level triggered interrupt, the interrupt is activated when the input signal is at a logic low (0) level.
High-Level Triggered Interrupt: In a high-level triggered interrupt, the interrupt is activated when the input signal is at a logic high (1) level.
