I/O

Question 1

I/O subsystems common concepts

Answer 1

Port 
Bus (daisy chain or shared direct access)
Controller (host adapter)
I/O instructions control devices
Devices have addresses, used by 
Direct I/O instructions
Memory-mapped I/O

OS works with device drivers (not controllers)

Question 2

Polling

Answer 2

Each interrupt is numbered; polling chks status
Determines state of device
command-ready, busy, error
Can run another device while polling

Question 3

General architecture for I/O device

Answer 3

Control registers
Command registers
Status registers
Buffer (read, write, handles timing differences)

Question 4

Interrupts

Answer 4

I/O device driver initiate I/O
Input ready, output complete, or error generates interrupt signal

CPU interrupt request line triggered by I/O device
CPU transfers control to interrupt handler
Interrupt handler receives interrupts
Interrupt handler processes data, returns from interrupt
CPU resumes processing of interrupted task

Question 5

Maskable interrupt

Answer 5

Maskable to ignore or delay some interrupts
Interrupt vector to dispatch interrupt to correct handler
Based on priority, some nonmaskable
Interrupt mechanism also used for exceptions

Question 6

Direct Memory Access

Answer 6

Used to avoid programmed I/O for large data movement
Requires DMA controller
Bypasses CPU to transfer data directly between I/O device and memory

Question 7

Busy-wait cycle

Answer 7

Same as polling, a check status command
if (CMD)
    busy = 1;
while (1)
     {WAIT, do I/O stuff}

Question 8

when does cpu check for interrupt

Answer 8

end of every instruction

Question 9

how can interrupts be disabled

Answer 9

disabled by CLI (clear interrupts)

enabled by STI (set interrupts)