HDL (Verilog) Flashcards
1
Q
Structural description
A
Textual replacement for schematic
Hierarchical composition of modules from primitives
2
Q
Bahavioural description
A
Describe what module does, not how
Synthesis genetates circuit for module
3
Q
Bitwise NOT
A
~a
4
Q
Bitwise AND
A
a & b
5
Q
Bitwise OR
A
a | b
6
Q
Bitwise XOR
A
a ^ b
7
Q
Bitwise XNOR
A
a ~^ B
8
Q
~a
A
Bitwise NOT
9
Q
a & b
A
Bitwise AND
10
Q
a | b
A
Bitwise OR
11
Q
a ^ b
A
Bitwise XOR
12
Q
a ~^ B
A
Bitwise XNOR
