Based on Test 1 Q1 Flashcards
List 4 ‘acceptable’ outputs of a robust system
- Power
- Data integrity
- Availability
- Security
Name ‘unforseen’ inputs that can affect a robust system.
- Defects/Process variation/Degraded transistors
- Design errors
- Software failures
- Malicious attacks
- Human error
- Software failures
Name attributes required for Robust (dependable) System Design for avoidance of problems
- Design validation/thorough test h/w + s/w
- Infant morality screening
- Transient error avoidance
What do the abbreviations CBM stand for?
Condition based monitoring
What do the abbreviation PHM stand for?
Prognostic health monitoring
What two types of models are associated with CBM and PHM?
Data driven reliability population based models.
Physics of failure (POF) models
Moore’s Law (scaling) affects what 3 aspects of a transistor and by how much?
- Gate dimensions scaled down by 30%
- Gate oxide thickness scales
- Vdd and Vt scaled
What 3 performance parameters directly relate with 3 aspects of a transistor affected by Moore’s law and what is the relative change?
Transistor density doubled — more capability/funcionality
Faster transistor — higher performance, lower active power
What is the
ITRS
International Technology Roadmap for Semiconductors
Why do actual (scaled) technology nodes lag ITRS predictions in automotive electronics?
Meeting Quality, Reliability and Environmental Demands
What 2 words describe the design process from specification to final product?
Transformation and optimization
What is a netlist?
Machine readable ‘soft model’ of a circuit in terms of function calls to components libraries together with a linked list.
How does verification differ from validation of complex ICS?
Verification ensures by simulation that the netlist meets the designer’s intent.
Validation (testing) checks that the final product does the job that it was intended to do in the specification.
For a system to be fault tolerant, it must be able to…
… detect ,diagnose, confine, mask, copensate and recover from faults.
What are 2 major chellenges for testing ICs?
Complexity and the test access.
