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LOGIC > FINALS 50 SET A > Flashcards

FINALS 50 SET A Flashcards

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1
Q

It is a system by which certain data or information is represented in numerical pattern.
a. system representation
b. digital system
c. analog system
d. none of these

A

d. none of these

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2
Q

A datapath, when combined with the control unit, forms a component referred to as ______.
a. central processing unit
b. input unit
c. output unit
d. memory unit

A

a. central processing unit

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3
Q

The equivalent of the decimal number 7562.45 in the octal numbering system is _________
a. 11612.646
b. 16612.346
c. 11612.346
d. 6612.436

A

b. 16612.346

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4
Q

The decimal number 175.175, when converted to binary, is ______
a. 1 1 1 1 0 1 0 1 . 1 0 1
c. 1 0 1 0 1 1 1 1 . 0 0 1
b. 1 0 1 0 1 0 1 1 . 0 0 1
d. 1 0 1 1 1 1 1 1 . 0 1 0

A

c. 1 0 1 0 1 1 1 1 . 0 0 1

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5
Q

Using the 2’s complement method, the result of subtracting 11011101 from 10100110 is _______
a. – 0 0 0 1 0 1 1 1
c. – 0 0 1 1 0 1 1 1
b. 0 0 1 1 0 1 1 1
d. – 0 0 1 0 0 1 0 1

A

c. – 0 0 1 1 0 1 1 1

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6
Q

Each of the following 4 numbers has a different base. Which of the four numbers have the same value in decimal ?
(a) 20225
(b) 120113
(c) 33124
(d) 19A12

a. b & d
c. a & c
b. c & d
d. none of these

A

d. none of these

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7
Q

Given two decimal numbers 694 and 835. Their sum in BCD is ________
a. 00111111001001
c. 0001010100101001
b. 01011111001001
d. none of these

A

c. 0001010100101001

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8
Q

The result of subtracting 654253758 from 740152368 is ___________
a. 6367541
c. 6267641
b. 6367641
d. 6367541

A

b. 6367641

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9
Q

The Boolean expression (X+Y+Z)’ = X’Y’Z’ is an example of which Law/Theorem?
a. Commutative Law
c. DeMorgan’s Theorem
b. Involution Law
d. Idempotent Theorem

A

c. DeMorgan’s Theorem

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10
Q

The Boolean expression (X’)’ is an example of which Law/Theorem?
a. Involution Law
c. Idempotent Law
b. Consensus Law
d. Inversion Law

A

a. Involution Law

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11
Q

The Boolean expression X + Y = Y + X is an example of which Law/Theorem?
a. Commutative Law
c. Idempotent Law
b. Involution Law
d. Associative Law

A

a. Commutative Law

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12
Q

This is the basic mathematics needed for the study of the logic design of digital systems.
a. Combinational Design
c. Boolean Algebra
b. Sequential Design
d. Quine-McCluskey Technique

A

c. Boolean Algebra

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13
Q

This has one or more inputs and one or more outputs which take on discrete values.
a. digital system
c. finite state machine
b. switching circuit
d. algorithmic state machine

A

b. switching circuit

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14
Q

This part of the design of digital system involves determining how to interconnect basic logic building blocks to perform a specific function
a. structural diagram
c. iterative design
b. behavioral design
d. logic design

A

d. logic design

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15
Q

The simplest form of the Boolean expression (a + b’ + c’)(a’ + c’) in product-of-sums form is _____
a. (a + c’)(c’ + b)
c. (a’ + c’)(c’ + b)
b. (a’ + c’)(c’ + b’)
d. none of these

A

b. (a’ + c’)(c’ + b’)

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16
Q

The reduced form of the Boolean expression (A’ + C)(A’ + C’)(A + B + C’D) is _______
a. A’B + A’C’D
c. AB’ + A’CD’
b. A’B’ + AC’D’
d. none of these

A

a. A’B + A’C’D

17
Q

The minterm expansion of the Boolean expression A’B’C’D’ + AC’D’ + B’CD’ + A’BCD + BC’D is
a. Σm(1, 2, 3, 6, 9, 10, 12, 14)
c. Σm(0, 2, 5, 7, 8, 10, 12, 13)
b. Σm(0, 1, 5, 7, 9, 10, 12, 13)
d. none of these

A

c. Σm(0, 2, 5, 7, 8, 10, 12, 13)

18
Q

What logical reason/s can you give why NAND and NOR gates are considered universal gates?
a. they can appear anywhere in the circuit
c. they can imitate function of other gates
b. they can produce universal operation
d. they cannot be partial

A

c. they can imitate function of other gates

19
Q

A race condition happens in an R-S latch when ______
a. R = 0 and S = 0
c. R = 0 and S = 1
b. R = 1 and S = 0
d. none of these

A

d. none of these

20
Q

This is the time needed by a gate in processing its input signals before the output signal can be generated
a. setup time
c. hold time
b. threshold time
d. none of these

A

d. none of these

21
Q

Which of the following does not belong to the group?
a. AND gate
c. Buffer
b. OR gate
d. Inverter

A

c. Buffer

22
Q

What code is used in labeling the cells of a K-map?
a. gray code
c. excess-3 code
b. BCD code
d. two-out-of-five code

A

a. gray code

23
Q

What will happen if the function v(w+x+y)z would be implemented using NOR gates?
a. Not possible using NOR gates
c. Six NOR gates will be used
b. given function must be implemented
using OR and NAND gates
d. none of these

A

c. Six NOR gates will be used

24
Q

The simplest form of the Boolean expression X’Z + W’XY’ + W(X’Y + XY’) in SOP form is
a. XZ’ + X’Y + W’XY
c. X’Z + XY’ + WX’Y
b. X’Z + XY’ + WXY’
d. none of these

A

c. X’Z + XY’ + WX’Y

25
Q

The binary signal at the inputs and outputs of any gate has one of two values, except during ____
a. threshold
c. transition
b. saturation
d. steady-state

A

c. transition

26
Q

This is a diagram made up of squares, with each square representing one minterm of the function
that is to be minimized
a. K-Map
c. Truth Table
b. Prime-Implicant Chart
d. Flowchart

A

a. K-Map

27
Q

In a 4-variable map, which of the following is not true?
a. 8 adjacent squares represent a 1-literal term
c. 4 adjacent squares represent a 3-literal term
b. 1 square represents a 4-literal term
d. 16 adjacent squares produce a function F = 1

A

c. 4 adjacent squares represent a 3-literal term

28
Q

Two adjacent 1’s form a prime implicant, provided that they are not within a group of ______
a. two adjacent squares
c. four adjacent squares
b. three adjacent squares
d. none of these

A

c. four adjacent squares

29
Q

The simplest expression (in sum-of-products form) for the function F(A,B,C,D,E) =
Σm (1,3,5,7,8,12,15,18,19,22,23,24,27,28,31) is
a. ABE + CD’E + AB’D+ADE+BD’E’
c. ABE + CD’E + AB’D+A’DE+BD’E’
b. A’B’E + CDE + AB’D + ADE + BD’E’
d. none of these

A

b. A’B’E + CDE + AB’D + ADE + BD’E’

30
Q

Use K-map to find the minimum SOP of F(W,X,Y,Z) = ΠM (0,2,4,6,8,10,12,14)
a. F = Z
c. F = W’Z
b. F = Z’
d. none of these

A

b. F = Z’

31
Q

Simplify the Expression (wx + yz)(w’y’+xz’) using Boolean Algebra:
a. w’x’y’
c. wx’z
b. w’xz
d. wxz’

A

d. wxz’

32
Q

Given the function F(a,b,c,d) = ΠM(1,3,5,9,12,14,15) determine its canonical form.
a. F = M1 + M3 + M5 + M9 + M12 + M14 + M15
c. F = m1m3m5m9m12m14m15
b. F = m1 + m3 + m5 + m9 + m12 + m14 + m15
d. F = M1M3M5M9M12M14M15

A

d. F = M1M3M5M9M12M14M15

33
Q

A Boolean function has a minterm expansion of F(W,X,Y,Z) =
Σm(1,3,4,5,9,10,11,12,13,14,15). Determine the essential prime implicants.
a. XY’
c. X’Z
b. WY
d. none of these

A

a. XY’

34
Q

This element of the ASM chart is connected by directed edges indicating the sequential precedence and evolution of the states as the machine operates.
a. decision box
c. conditional box
b. state box
d. all of these

A

d. all of these

35
Q

This element of the ASM chart describes the effect of an input on the control subsystem.
a. decision box
c. conditional box
b. state box
d. none of these

A

a. decision box

36
Q

This is a device in which the output depends in some systematic way on variables
other than the immediate inputs to the device.
a. combinational circuit
c. state machine
b. programmable logic device
d. programmable logic array

A

c. state machine

37
Q

This is a graph with labeled nodes and arcs; the nodes are the states and the arcs are the possible
transitions between states
a. Nodal diagram
c. Venn diagram
b. state diagram
d. none of these

A

b. state diagram

38
Q

The master-slave is a pulse-triggered flip-flop and is indicated as such with a right angle symbol called a ______________
a. dynamic input indicator
c. postponed output indicator
b. static pulse indicator
d. none of these

A

c. postponed output indicator

39
Q

The control sequence and datapath tasks of a digital system are specified by means of a ___.
a. software algorithm
c. program control unit
b. hardware algorithm
d. arithmetic & logic unit

A

b. hardware algorithm

LOGIC (2 decks)

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