Exam #3 Review Part 1

Question 1

Instruction Latency vs Throughput

Answer 1

Instruction Latency: The inherent execution time for an instruction

Throughput: Also called bandwidth. Another measure of performance, it is the number of tasks completed per unit time.

Question 2

Pipeline Stages

Answer 2

Stage 1: IF(Instruction Fetch)
-IM

Stage 2: ID(Instruction Decode)
-Reg(Read)

Stage 3: EX(Execute)
-ALU

Stage 4: MEM(Data Memory Access)
-DM

Stage 5: WB(Write-Back)
-Reg(Write)

Question 3

Clock Cycles

Answer 3

The time for one clock period, usually of the processor clock, which runs at a constant rate.

Question 4

Hazards

Answer 4

Data Hazard

• Also called a pipeline data hazard
• When a planned instruction can’t execute in proper clock cycle because data that is needed to execute the instruction is not yet available.

Branch Hazard

• Control Hazard
• When proper instruction can’t execute in proper pipeline clock cycle because instruction that was fetched is not one that’s needed. Flow of instruction addresses is not what pipeline expected.

Question 5

Superscalar Processors

Answer 5

An advanced pipelining technique that enables to execute more than one instruction per clock cycle by selecting them during execution.