Exam 2 - Chapter 7 Flashcards
CPU & Memory Are?
CPU requires memory access for every instruction
CPU: Major Components
ALU (arithmetic logic unit)
CU (control unit)
CPU - ALU (arithmetic logic unit)
Performs calculations and comparisons
CPU - CU (control unit)
Performs Fetch/Execute cycle - flag conditions
CPU: Sub Components
Memory Management Unit
I/O Interface
CPU Sub Component: Bus Interface Unit
Memory Management Unit & I/O Interface combined
CPU - FLAGS
Arithmetic carry & overflow - power failure - internal comp error - can be grouped into status registers
BUS
Bridge between Memory & CPU
physical connection to trans data from one comp sys to another
Bus signals or types
4 kinds: data - addressing - control signals - power (sometimes)
Bus (dedicated)
Internal to CPU and do not interface with outside world
Bus (general)
PCI express - USB - IDE - SATA
Line
Each conductor in the bus
Bus Categories
Parallel - serial
Transmission directions
Simplex - Half Duplex - Full Duplex
Simplex
unidirectional
Half Duplex
bidirectional - one direction at a time
Full Duplex
bidirectional simultaneously
Bus Connections
Point-to-Point (single source to single destination)
Multipoint (multiple points connected) aka broadcast bus or multidrop bus
Parallel
high throughput - all bits of word are trans simultaneously
Expensive & space hog
affected by radio-generated electrical interference
used for short distances ie CPU busses and motherboards
Serial
1 bit transmitted at a time
single data line pair
few control lines
can be higher throughput than parallel due to non interference
Point to Point
USB port to printer - CU to ALU
Multipoint Broadcast BUS Ethernet
Multiple computers - network printer - network storage
Multipoint bus
CPU - Memory - Disk Controller - Video Controller
Registers
Single permanent storage location within the CPU used for a particular defined purpose.
Use of Registers
Scratchpad for currently executing program- Holds data needed quickly or frequently
Stores information about status of CPU and currently executing program- Address of next program instruction -Signals from external devices - i/o - cds - vid card etc.
General Purpose Register
User- or program-visible registers
Hold intermediate results or data values - e.g. - loop counters
Equivalent to LMC?s calculator
Typically several dozen in current CPUs
MDR Register
Data - no instructions
A memory buffer register.
Status Register
Status of CPU & currently executing program
Flags (one bit Boolean variable) to track conditions like arithmetic carry and overflow - power failure - internal computer error
MAR Register
have/holds address of memory location w/data or instruction
IR Register
Stores instruction fetched from memory - the instruction currently being executed by comp
Program Counter Register
AKA instruction pointer (IP)
Holds the address of the current instruction being executed.
Accumulator
is equivalent to the calculator in lmc. Cpus provide several accumulators in a general purpose register88
Memory Location
Unique addressing ie mail boxes in LMC
Memory Operation
MAR gets address from instruction
CPU decides store or retrieval
Transfer between MDR & Memory
MDR is a two way register
RAM
Random Access Memory
DRAM (Dynamic RAM)
Volatile - common - cheap - must be refreshed 1000’s X each second
SRAM (Static RAM)
Volatile - faster - more expensive - small amounts used in cache memory
Cache Memory
static ram memory that is used for high speed access
ROM
Read Only Memory - NON-Volatile - holds firmware software ie bios
Flash Memory
NON-Volatile - secondary storage - portable - slower rewrite
Fetch-Execute Cycle
2-cycle process since both instructions & data are in memory
Fetch
Decode or find instruction - load from memory into register & signal ALU
Execute
Performs operation that instruction requires - move/transform data
Cycle - Load
Transfer address PC to MAR Transfer instruction MDR to IR Load instruction IR (address) to MAR Data copied to accumulator MDR to A Program Counter incremented PC + 1 = PC
Cycle - Store
Transfer address PC to MAR Transfer instruction MDR to IR Load instruction IR (address) to MAR Accumulator copies data into MDR. A to MDR Program Counter incremented PC + 1 = PC
Cycle - Add
Transfer address PC to MAR Transfer instruction MDR to IR Load instruction IR (address) to MAR MDR contents added to accumulartor contents. A + MDR to A Program Counter incremented PC + 1 = PC
Instruction Classifications
Data Movement (load - Store)
Arithmetic (+ - * /)
Boolean (T/F - Y/N)
Single operand (++ –)
Priviledged Instruction
Operating Instructions HALT I/O Mem Mgmt Encryption & Decryption Sys Admin
App level Instructions
aka user acessible instructions
User Space
programs that execute w/o priviledges execute in user space
OPCODE
Task
Source OPERAND
Addresses
Result OPERAND
Addresses - location of data - explicit (included in instruction) - implicit default assumed.
