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IT 254 - Illinois State University > Exam 2 - Chapter 7 > Flashcards

Exam 2 - Chapter 7 Flashcards

1
Q

CPU & Memory Are?

A

CPU requires memory access for every instruction

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2
Q

CPU: Major Components

A

ALU (arithmetic logic unit)

CU (control unit)

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3
Q

CPU - ALU (arithmetic logic unit)

A

Performs calculations and comparisons

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4
Q

CPU - CU (control unit)

A

Performs Fetch/Execute cycle - flag conditions

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5
Q

CPU: Sub Components

A

Memory Management Unit

I/O Interface

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6
Q

CPU Sub Component: Bus Interface Unit

A

Memory Management Unit & I/O Interface combined

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7
Q

CPU - FLAGS

A

Arithmetic carry & overflow - power failure - internal comp error - can be grouped into status registers

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8
Q

BUS

A

Bridge between Memory & CPU

physical connection to trans data from one comp sys to another

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9
Q

Bus signals or types

A

4 kinds: data - addressing - control signals - power (sometimes)

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10
Q

Bus (dedicated)

A

Internal to CPU and do not interface with outside world

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11
Q

Bus (general)

A

PCI express - USB - IDE - SATA

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12
Q

Line

A

Each conductor in the bus

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13
Q

Bus Categories

A

Parallel - serial

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14
Q

Transmission directions

A

Simplex - Half Duplex - Full Duplex

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15
Q

Simplex

A

unidirectional

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16
Q

Half Duplex

A

bidirectional - one direction at a time

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17
Q

Full Duplex

A

bidirectional simultaneously

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18
Q

Bus Connections

A

Point-to-Point (single source to single destination)

Multipoint (multiple points connected) aka broadcast bus or multidrop bus

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19
Q

Parallel

A

high throughput - all bits of word are trans simultaneously
Expensive & space hog
affected by radio-generated electrical interference
used for short distances ie CPU busses and motherboards

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20
Q

Serial

A

1 bit transmitted at a time
single data line pair
few control lines
can be higher throughput than parallel due to non interference

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21
Q

Point to Point

A

USB port to printer - CU to ALU

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22
Q

Multipoint Broadcast BUS Ethernet

A

Multiple computers - network printer - network storage

23
Q

Multipoint bus

A

CPU - Memory - Disk Controller - Video Controller

24
Q

Registers

A

Single permanent storage location within the CPU used for a particular defined purpose.

25
Q

Use of Registers

A

Scratchpad for currently executing program- Holds data needed quickly or frequently
Stores information about status of CPU and currently executing program- Address of next program instruction -Signals from external devices - i/o - cds - vid card etc.

26
Q

General Purpose Register

A

User- or program-visible registers
Hold intermediate results or data values - e.g. - loop counters
Equivalent to LMC?s calculator
Typically several dozen in current CPUs

27
Q

MDR Register

A

Data - no instructions

A memory buffer register.

28
Q

Status Register

A

Status of CPU & currently executing program
Flags (one bit Boolean variable) to track conditions like arithmetic carry and overflow - power failure - internal computer error

29
Q

MAR Register

A

have/holds address of memory location w/data or instruction

30
Q

IR Register

A

Stores instruction fetched from memory - the instruction currently being executed by comp

31
Q

Program Counter Register

A

AKA instruction pointer (IP)

Holds the address of the current instruction being executed.

32
Q

Accumulator

A

is equivalent to the calculator in lmc. Cpus provide several accumulators in a general purpose register88

33
Q

Memory Location

A

Unique addressing ie mail boxes in LMC

34
Q

Memory Operation

A

MAR gets address from instruction
CPU decides store or retrieval
Transfer between MDR & Memory
MDR is a two way register

35
Q

RAM

A

Random Access Memory

36
Q

DRAM (Dynamic RAM)

A

Volatile - common - cheap - must be refreshed 1000’s X each second

37
Q

SRAM (Static RAM)

A

Volatile - faster - more expensive - small amounts used in cache memory

38
Q

Cache Memory

A

static ram memory that is used for high speed access

39
Q

ROM

A

Read Only Memory - NON-Volatile - holds firmware software ie bios

40
Q

Flash Memory

A

NON-Volatile - secondary storage - portable - slower rewrite

41
Q

Fetch-Execute Cycle

A

2-cycle process since both instructions & data are in memory

42
Q

Fetch

A

Decode or find instruction - load from memory into register & signal ALU

43
Q

Execute

A

Performs operation that instruction requires - move/transform data

44
Q

Cycle - Load

A 
Transfer address PC to MAR
Transfer instruction MDR to IR
Load instruction IR (address) to MAR
Data copied to accumulator MDR to A
Program Counter incremented PC + 1 = PC
45
Q

Cycle - Store

A 
Transfer address PC to MAR
Transfer instruction MDR to IR
Load instruction IR (address) to MAR
Accumulator copies data into MDR.  A to MDR
Program Counter incremented PC + 1 = PC
46
Q

Cycle - Add

A 
Transfer address PC to MAR
Transfer instruction MDR to IR
Load instruction IR (address) to MAR
MDR contents added to accumulartor contents.  A + MDR to A
Program Counter incremented PC + 1 = PC
47
Q

Instruction Classifications

A

Data Movement (load - Store)
Arithmetic (+ - * /)
Boolean (T/F - Y/N)
Single operand (++ –)

48
Q

Priviledged Instruction

A 
Operating Instructions
HALT
I/O
Mem Mgmt
Encryption & Decryption
Sys Admin
49
Q

App level Instructions

A

aka user acessible instructions

50
Q

User Space

A

programs that execute w/o priviledges execute in user space

51
Q

OPCODE

A

Task

52
Q

Source OPERAND

A

Addresses

53
Q

Result OPERAND

A

Addresses - location of data - explicit (included in instruction) - implicit default assumed.

IT 254 - Illinois State University (4 decks)

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