Electronics Manufacturing (PCBs + ICs) Flashcards
Global chip shortage due to COVID
- Manufacturing delays: Major disruptions in global supply chains, as lockdowns and restrictions halted production at semiconductor fabrication plants, especially in key locations like Taiwan, South Korea, and China. Many manufacturing facilities faced temporary closures or reduced capacity, leading to severe supply shortages.
- Logistics and Transportation Delays: Even when factories were operational, disruptions in logistics and transportation (e.g., port closures, limited cargo space) delayed the shipping of essential raw materials, tools, and chips. This caused a bottleneck in the availability of chips across multiple industries, including automotive and consumer electronics.
Rising Global Demand for Electronics during 2020 and its effects on the chip manufacturing industry
- Increased Demand for Remote Work and Entertainment: As the pandemic forced people to work from home and engage in online activities, there was a massive surge in demand for devices like laptops, smartphones, gaming consoles, and home networking equipment. This spike in demand further exacerbated the chip shortage, as manufacturers struggled to keep up
- Automotive Industry Impact: Automakers initially reduced chip orders during the early stages of the pandemic, anticipating lower car sales. However, as demand rebounded faster than expected, they found themselves in fierce competition for chips, leading to severe shortages in the automotive sector and production delays
Integrated Device Manufacturing (IDM) business model
- Business Model: IDMs handle both the design and manufacturing of semiconductor chips. They own their fabrication facilities (fabs) and control the entire process from design to production and sometimes even marketing.
- Key Players: Examples of IDMs include Intel, Samsung, and Texas Instruments. These companies design and manufacture their own chips while often producing chips for other companies.
- Advantages:
- Control Over Supply Chain: IDMs have tighter control over their manufacturing, enabling faster integration of design and fabrication for specific product requirements.
- Product Optimization: Since IDMs manage both design and manufacturing, they can optimize products for performance, power efficiency, and cost.
- Challenges:
- Capital Intensive: Maintaining both design and fabrication facilities requires significant investment in both capital and human resources. IDMs face high costs to stay competitive with specialized foundries like TSMC.
“Pure Play” chip manufacturing business model
- Business Model: Pure play foundries specialize solely in manufacturing semiconductor chips but do not design or sell their own chips. They produce chips for other companies that focus on chip design but lack fabrication facilities.
- Key Players: Examples include TSMC (Taiwan Semiconductor Manufacturing Company) and GlobalFoundries. These companies provide manufacturing services to fabless companies like AMD, Qualcomm, and Nvidia.
- Advantages:
- Focus: Pure play foundries can focus exclusively on advancing manufacturing technology and achieving high yields, which benefits fabless companies.
- Scalability: They can serve a wide range of customers, offering flexibility in volume and specialized manufacturing processes.
- Challenges:
- Heavy Competition: Pure play foundries often compete on advanced technology nodes (e.g., 7nm, 5nm), leading to large investments in R&D and new fabrication facilities.
Three companies capable of making modern chips
Foundry
1) Samsung (IDM)
2) TSMC: Taiwan Semiconductor Manufacturing Company (pure-play)
3) Intel (IDM)
“Foundry Overload” during COVID
Major semiconductor foundries like TSMC and Samsung were operating at full capacity to meet the surge in demand. However, the increased workload pushed lead times for chip manufacturing from a few months to over a year in some cases
The shortage was particularly acute for chips built on older process nodes (e.g., 28nm and 65nm), which are commonly used in automotive and industrial sectors. Foundries had largely transitioned to advanced nodes (e.g., 7nm, 5nm) and thus had limited capacity for older technologies
Government Intervention in the Silicon Industry during COVID
In response to the chip shortages, several governments announced initiatives to boost domestic semiconductor manufacturing. For example, the U.S. CHIPS Act aimed to incentivize chip manufacturing within the U.S. to reduce reliance on foreign supply chains
Companies began reassessing their supply chains to diversify sourcing and reduce dependency on a few critical suppliers. This led to increased investments in reshoring manufacturing facilities and collaborations between governments and private companies to avoid future shortage
“Fab” in VLSI
Definition: A fab (short for fabrication plant) is a factory where semiconductor devices, such as integrated circuits (ICs), are manufactured. These facilities contain the specialized equipment needed to process silicon wafers and create transistors, memory chips, and other components.
Scope: A fab can be owned by companies that both design and manufacture their own chips. For example, Intel and Samsung own fabs where they produce their proprietary semiconductor products.
Example: Intel owns its fabs to manufacture its own processors. Companies that design and manufacture in-house are referred to as IDMs (Integrated Device Manufacturers).
“Foundry” in VLSI
Definition:
A foundry is a type of semiconductor fab that specializes in manufacturing chips for third-party clients. Foundries do not design their own chips; instead, they produce chips that are designed by fabless companies, such as Apple, AMD, and Nvidia.
Scope:
Foundries focus solely on the manufacturing aspect of semiconductor production and offer their services to fabless semiconductor companies. This allows fabless companies to concentrate on design while outsourcing the complex and expensive task of fabrication to foundries.
Example: TSMC (Taiwan Semiconductor Manufacturing Company) is the world’s largest pure-play foundry, manufacturing chips for various fabless companies.
Fab v. Foundry in VLSI
A fab is any semiconductor fabrication plant, whereas a foundry is a type of fab that manufactures chips for other companies, typically fabless semiconductor designers. The foundry business model enables companies to focus on design while outsourcing manufacturing to specialized facilities
Long Term impact of COVID on the “supply chain resiliance” of the silicon industry
Companies are now diversifying their supply chains to avoid reliance on a single region or supplier, since much of the world’s semiconductor production was concentrated in East Asia, especially Taiwan and South Korea. Now, companies are seeking to reduce this geographic dependency by establishing more distributed supply chains
Countries like the United States and regions like the European Union are pushing to bring more chip manufacturing onshore with programs such as the U.S. CHIPS Act and EU’s Chip Initiative. These initiatives offer incentives for building new fabs locally
Impact of COVID on fab location/geographic distribution
Foundries like TSMC and Intel have announced plans to build new fabrication facilities in the U.S. and Europe. For instance, Intel plans to build fabs in Ohio and Arizona, while TSMC is constructing new facilities in Arizona. These projects are aimed at increasing the geographic distribution of semiconductor manufacturing and reducing reliance on Asia
Inventory Buffers
Companies are now maintaining higher inventories of critical components to avoid future shortages. Before the pandemic, the industry relied heavily on just-in-time manufacturing, where components were produced and delivered right when they were needed. The chip shortages during the pandemic exposed the vulnerabilities of this system, leading to a shift toward holding buffer inventories
Digital-Transformation in Silicon Industry Supply chains
The pandemic highlighted the lack of visibility many companies had into their supply chains. In response, there is a growing emphasis on supply chain transparency using digital tools such as AI and blockchain to track components and predict disruptions. These technologies are being integrated to provide better foresight and enable more proactive decision-making.
Lead Time for advanced nodes
The pandemic revealed the challenges of producing advanced semiconductors with smaller process nodes. The global shortage of chips, especially for 28nm and older nodes, underscored the importance of long-term planning for capacity expansion. This includes investments not just in leading-edge nodes but also in older nodes that are still critical for sectors like automotive and industrial devices
Climate Resistant manufacturing
Climate change is an emerging concern for chipmakers as extreme weather events (e.g., droughts in Taiwan, floods in Texas) further threaten semiconductor production. Companies are increasingly factoring in climate resilience when making decisions about where to build new fabs. For instance, fabs require large amounts of water, so companies are considering water availability and sustainability in their long-term site planning
Reshoring v. Nearshoring
Both reshoring and nearshoring aim to improve supply chain reliability, but they differ in terms of geographic location and cost. Reshoring brings manufacturing back home, often at a higher cost, while nearshoring moves production to neighboring countries, offering a balance between cost savings and reduced logistical risks. Both strategies are responses to increasing demand for more resilient, secure, and agile supply chains
Basic Silicon Manufacturing Steps
1) Silicon material is melted into a silicon ingot
2) Silicon ingot is sliced into wafers
3) A series of 20-30 proprietary steps are used to “pattern” the wafers
4) The wafer is tested and diced (cutouts that did not pass testing are rejected)
5) Silicon cutouts are ‘bonded’ into a package
6) The entire die package is retested before being shipped
*Direct relationship between the number of steps used and the cost of the chip
Shorts as a manufacturing defect
Description: Shorts occur when unintended connections form between different conducting regions, such as the gate, source, or drain terminals of a transistor. This typically happens due to improper lithography, contamination, or defects in the etching process.
Impact: Shorts cause incorrect electrical behavior, such as the transistor being permanently on or off, leading to functional failure.
Prevention/Mitigation:
Improved Lithography: Use advanced lithography techniques, such as Extreme Ultraviolet (EUV) lithography, to enhance patterning precision.
Design Rule Checks (DRC): Ensure proper spacing between metal lines and other features during layout design to prevent shorts.
Defect Inspection: Use optical or electron microscopy to inspect wafers and detect shorts early.
Opens as a manufacturing defect
Description: Opens occur when there is a discontinuity in the conductive paths of the transistor, such as broken interconnects between the source, drain, or gate terminals.
Impact: The transistor cannot conduct properly, leading to signal loss or failure in logic circuits.
Prevention/Mitigation:
Process Control: Ensure uniform material deposition and etching to avoid incomplete or broken interconnects.
Redundancy in Design: Use redundant vias and interconnect layers in critical paths to provide alternative conduction routes if a break occurs.
Post-fabrication Testing: Perform electrical tests like Automatic Test Equipment (ATE) to identify broken connections.
Gate-Oxide Defects in VLSI
Description: Gate oxide defects involve imperfections in the thin insulating layer between the transistor’s gate and channel. These can result from contamination or defects during oxide growth or deposition.
Impact: A defective gate oxide layer can cause gate leakage (current passing through the gate), reduce the transistor’s ability to turn on/off, or lead to early transistor breakdown.
Prevention/Mitigation:
Clean Manufacturing Environment: Use cleanrooms and advanced chemical cleaning processes to minimize contamination.
Oxide Thickness Control: Maintain strict control over the oxide growth process to ensure uniformity and avoid thin or defective regions.
Passivation Layers: Add protective passivation layers to shield the gate oxide from external contamination or damage.
Defective Threshold voltage in VLSI
Description: Variations in the threshold voltage (Vth), which defines the voltage at which a transistor switches on or off, can arise due to doping inconsistencies, oxide thickness variations, or manufacturing defects.
Impact: Transistor behavior can become unpredictable, leading to timing issues, power leakage, and signal integrity problems.
Prevention/Mitigation:
Doping Control: Ensure uniform doping levels during implantation and annealing processes to minimize threshold voltage variation.
Process Calibration: Use advanced process control (APC) techniques to monitor and adjust the manufacturing process in real time.
Statistical Process Control (SPC): Track Vth variations across different chips and wafers, allowing manufacturers to identify process drifts.
Latch-Up Defect in VLSI
Description: Latch-up occurs when parasitic elements within a transistor (like parasitic p-n-p-n structures) form unintended feedback loops, causing high current to flow between power and ground, potentially damaging the chip.
Impact: This can lead to a short circuit, overheating, and permanent chip failure.
Prevention/Mitigation:
Guard Rings: Use guard rings around sensitive circuit areas to isolate the parasitic components and prevent latch-up.
Substrate Biasing: Apply proper biasing to the substrate to reduce the formation of parasitic paths.
Design Practices: Implement layout techniques that minimize the interaction between p-n-p and n-p-n parasitic elements.
Over-doping Manufacturing Defect
Definition: Over-doping happens when too many dopant atoms are introduced into the semiconductor, exceeding the desired concentration.
Causes:
Excessive Ion Implantation: If the ion implantation energy or dosage is too high, more dopant atoms than necessary are implanted into the substrate.
Uncontrolled Diffusion: Excessive diffusion of dopant atoms, often due to higher-than-expected temperatures or diffusion times, can lead to over-doping.
Masking Errors: Defects or misalignment in photolithography masks can expose areas that were not intended to be doped, leading to unwanted doping in those regions.