Digital Design Modeling (SystemVerilog + ) Flashcards
Hardware Description Languages
Specialized language used to describe the structure and behavior of electronic circuits.
Allows you to automate both simulation and synthesis.
Logic Simulation
Inputs are applied to a module and the outputs are checked to verify that the model operates correctly. (Basically looking at the timing diagrams and making sure that everything looks as expected)
Logic Synthesis
The textual description of a module is transformed into logic gates
HDL synthesizers recognize certain idioms and turn them into specific sequential circuits
Other coding styles may simulate correctly, but synthesize into circuits with blatant or subtle errors
Note: Use the proper idioms to describe registers and latches
Synthesizable Design
Means that the design (as described in the code) can actually be implemented using logic gates within the given parameters
Division and modulus operations are often unsynthesizable
1) Avoid High-Level Constructs: Avoid using constructs that are unsupported by synthesis tools, such as dynamic data types, certain procedural blocks, and high-level features. Dynamic arrays, queues, classes, assertions, initial blocks, and forever loops are typically not synthesizable.
Use Static arrays instead of dynamic arrays.
2) Remove Delays (#): Avoid using # delays or wait statements in synthesizable code. Synthesis tools do not support delays or timing-based constructs, which are useful in simulation but not in actual hardware design.
3) Use Proper Sensitivity Lists: Use always_comb for combinational logic and always_ff for sequential logic with the correct clock and reset signals.
4) Avoid Infinite Loops: Avoid infinite loops (forever, while) in synthesizable code. Such loops are used for simulation purposes but cannot be translated to hardware.
5) Use Fixed-Size Arrays: Use fixed-size arrays instead of dynamic arrays, queues, or associative arrays. Synthesis tools need to know the exact size of the hardware they are generating.
6) Use Blocking and Non-blocking Assignments Appropriately: Use blocking assignments (=) in combinational logic and non-blocking assignments (<=) in sequential logic.
7) Avoid Using System Functions: Avoid using system tasks or functions like $display, $random, $monitor, and assertions (assert). These are simulation-only constructs.
8) Avoid Mixed Edge Sensitivity: Ensure that flip-flops are triggered on a single edge (either rising or falling edge) and do not mix both edges in the same block.
9) Proper Reset Logic: Always include a reset signal to initialize flip-flops, and make sure the reset logic is synchronous or asynchronous depending on design needs.
10) Avoid Full Case and Parallel Case Compiler Directives: Avoid using full_case and parallel_case compiler directives unless you are sure about the implications on synthesis. These can lead to unintended synthesis behavior, such as ignoring default cases or optimizations.
Behavioral Level System Descriptions
Describes how the outputs are computed as functions of the inputs
Structural Level System Descriptions
Describes how a module is composed of simpler modules of basic primitives (gates or transistors)
Top-Down Design
Starting from the SOI/mission and breaking it down into more granular components (like reverse engineering)
Bottom-Up Design
Piecing together smaller systems to build a larger, more relevant SOI
History of System Verilog
- Verilog was developed by Phil Moorby at Gateway Design Automation as a proprietary language for logic simulation in 1984
- Gateway is acquired by Cadence in 1989
- Made an open standard in 1990 under the control of Open Verilog International
- Became an IEEE standard in 1995 and Updated in 2001 [IEEE1364-01]
- In 2005, it was updated again with minor clarifications
- Then SystemVerilog [IEEE 1800-2009] was introduced in 2009
-Streamlines many of the annoyances of Verilog and adds high-level programming language features that have proven useful in verification
Module
System Verilog Term.
Refers to a block of hardware with inputs and outputs.
Begins with a listing of the inputs and
outputs.
Continues with statements.
Assign Statement
Indicates combinational Logic
“logic” signals such as the inputs and outputs are
Boolean variables (0 or 1); They may also have
floating (z) and undefined values (x)
always ‘concurrent’, unlike variables in other programming languages where they can be re-assigned
Logic Type in system verilog
- Supersedes the “reg” type, which was a
perennial source of confusion in Verilog - should be used everywhere except on nets with
multiple drivers
Logic signals such as the inputs and outputs are
Boolean variables (0 or 1); They may also have
floating (z) and undefined values (x)
EXAMPLE:
module sillyfunction(input logic a, b, c,
output logic y);
assign y = ~a & ~b & ~c |
a & ~b & ~c |
a & ~b & c;
endmodule
Combinational Logic Operators
Used to build expressions that relate who ‘operands’ (a, b, x, y, etc). These expressions are needed for statements such as assign
~ indicates NOT
& indicates AND
| indicates OR
^ indicates XOR
Verilog Comments
// indicates a single line comment
/* */ indicated a multi-line comment
Operands in verilog
Represent a particular signal
Can be defined either in the inputs/outputs at the begining of the module
They are case sensitive (‘y’ is a completely different signal from ‘Y’)
Correct Implementation of Assign Statements
Syntax: assign [signal operand] = [logical expression]
*logical expressions combine operands using operators
EXAMPLE:
module gates(input logic [3:0] a, b,
output logic [3:0] y1, y2, y3, y4, y5);
/* Five different two-input logic
gates acting on 4 bit busses */
assign y1 = a & b; // AND
assign y2 = a | b; // OR
assign y3 = a ^ b; // XOR
assign y4 = ~(a & b); // NAND
assign y5 = ~(a | b); // NOR
endmodule
Correct implementation of conditional operators
/* 4-bit mux; selects one of two 4-bit
inputs d0 or d1
Equivalent to this expression:
If s = 1, then y = d1.
If s = 0, then y = d0.*/
module mux2_4 (input logic [3:0] d0, d1,
input logic s, output logic [3:0] y);
assign y = s ? d1 : d0;
endmodule
Conditional Operators
Syntax: assign [signal operand] = [condition] ? [expression 1] : [expression 2];
If the condition evaluates to TRUE (has a value of 1), the “expression 1” will be assigned to the signal. If the condition evaluates to FALSE (has a value of 0), the “expression 2” will be assigned to the signal.
Reduction Operators
Basically used to ‘demultiplex’ a bunch of signals and perform a logic operation on them at the same time.
Reduction operators imply a multiple-input
gate acting on a single bus
* |, ^, ~&, and ~| reduction operators are
available for OR, XOR, NAND, and NOR
Correct Implementation of Reduction Operators
module and8 (input logic [7:0] a,
output logic y);
assign y = & a;
// &a is much easier to write than
// assign y = a[7] & a[6] & a[5] & a[4]
// & a[3] & a[2] & a[1] & a[0];
endmodule
Correct Implementation of a 32 bit adder in system verilog
/* 32-bit adder */
module adder (a, b, y);
input logic [31:0] a;
input logic [31:0] b;
output logic [31:0] y;
assign y = a + b;
endmodule
Correct way to have nested conditional operators
/* */
module whatami(input logic [3:0] d0, d1, d2, d3,
input logic [1:0] s, output logic [3:0] y);
assign y = s[1] ? (s[0] ? d3 : d2)
: (s[0] ? d1 : d0);
endmodule
“Operator Precedence” in System Verilog
It’s like the “order of operations” in Math
Subtraction in System Verilog
There is no operator for it; just use compliment and addition
- } variable_name;
enumerators: The named values or states.
variable_name: The variable that will hold the enumerated value.
logic [n-1:0]: Optional, specifying the bit-width or encoding for the enumerators (if needed).
Benefits:
1) Readability
2) Type Safety
3) Error Detection
4) Automatic Handling of State Machines
5) Simplified Coding