Digital Design Modeling (SystemVerilog + ) Flashcards
Hardware Description Languages
Specialized language used to describe the structure and behavior of electronic circuits.
Allows you to automate both simulation and synthesis.
Logic Simulation
Inputs are applied to a module and the outputs are checked to verify that the model operates correctly. (Basically looking at the timing diagrams and making sure that everything looks as expected)
Logic Synthesis
The textual description of a module is transformed into logic gates
HDL synthesizers recognize certain idioms and turn them into specific sequential circuits
Other coding styles may simulate correctly, but synthesize into circuits with blatant or subtle errors
Note: Use the proper idioms to describe registers and latches
Synthesizable Design
Means that the design (as described in the code) can actually be implemented using logic gates within the given parameters
Division and modulus operations are often unsynthesizable
1) Avoid High-Level Constructs: Avoid using constructs that are unsupported by synthesis tools, such as dynamic data types, certain procedural blocks, and high-level features. Dynamic arrays, queues, classes, assertions, initial blocks, and forever loops are typically not synthesizable.
Use Static arrays instead of dynamic arrays.
2) Remove Delays (#): Avoid using # delays or wait statements in synthesizable code. Synthesis tools do not support delays or timing-based constructs, which are useful in simulation but not in actual hardware design.
3) Use Proper Sensitivity Lists: Use always_comb for combinational logic and always_ff for sequential logic with the correct clock and reset signals.
4) Avoid Infinite Loops: Avoid infinite loops (forever, while) in synthesizable code. Such loops are used for simulation purposes but cannot be translated to hardware.
5) Use Fixed-Size Arrays: Use fixed-size arrays instead of dynamic arrays, queues, or associative arrays. Synthesis tools need to know the exact size of the hardware they are generating.
6) Use Blocking and Non-blocking Assignments Appropriately: Use blocking assignments (=) in combinational logic and non-blocking assignments (<=) in sequential logic.
7) Avoid Using System Functions: Avoid using system tasks or functions like $display, $random, $monitor, and assertions (assert). These are simulation-only constructs.
8) Avoid Mixed Edge Sensitivity: Ensure that flip-flops are triggered on a single edge (either rising or falling edge) and do not mix both edges in the same block.
9) Proper Reset Logic: Always include a reset signal to initialize flip-flops, and make sure the reset logic is synchronous or asynchronous depending on design needs.
10) Avoid Full Case and Parallel Case Compiler Directives: Avoid using full_case and parallel_case compiler directives unless you are sure about the implications on synthesis. These can lead to unintended synthesis behavior, such as ignoring default cases or optimizations.
Behavioral Level System Descriptions
Describes how the outputs are computed as functions of the inputs
Structural Level System Descriptions
Describes how a module is composed of simpler modules of basic primitives (gates or transistors)
Top-Down Design
Starting from the SOI/mission and breaking it down into more granular components (like reverse engineering)
Bottom-Up Design
Piecing together smaller systems to build a larger, more relevant SOI
History of System Verilog
- Verilog was developed by Phil Moorby at Gateway Design Automation as a proprietary language for logic simulation in 1984
- Gateway is acquired by Cadence in 1989
- Made an open standard in 1990 under the control of Open Verilog International
- Became an IEEE standard in 1995 and Updated in 2001 [IEEE1364-01]
- In 2005, it was updated again with minor clarifications
- Then SystemVerilog [IEEE 1800-2009] was introduced in 2009
-Streamlines many of the annoyances of Verilog and adds high-level programming language features that have proven useful in verification
Module
System Verilog Term.
Refers to a block of hardware with inputs and outputs.
Begins with a listing of the inputs and
outputs.
Continues with statements.
Assign Statement
Indicates combinational Logic
“logic” signals such as the inputs and outputs are
Boolean variables (0 or 1); They may also have
floating (z) and undefined values (x)
always ‘concurrent’, unlike variables in other programming languages where they can be re-assigned
Logic Type in system verilog
- Supersedes the “reg” type, which was a
perennial source of confusion in Verilog - should be used everywhere except on nets with
multiple drivers
Logic signals such as the inputs and outputs are
Boolean variables (0 or 1); They may also have
floating (z) and undefined values (x)
EXAMPLE:
module sillyfunction(input logic a, b, c,
output logic y);
assign y = ~a & ~b & ~c |
a & ~b & ~c |
a & ~b & c;
endmodule
Combinational Logic Operators
Used to build expressions that relate who ‘operands’ (a, b, x, y, etc). These expressions are needed for statements such as assign
~ indicates NOT
& indicates AND
| indicates OR
^ indicates XOR
Verilog Comments
// indicates a single line comment
/* */ indicated a multi-line comment
Operands in verilog
Represent a particular signal
Can be defined either in the inputs/outputs at the begining of the module
They are case sensitive (‘y’ is a completely different signal from ‘Y’)
Correct Implementation of Assign Statements
Syntax: assign [signal operand] = [logical expression]
*logical expressions combine operands using operators
EXAMPLE:
module gates(input logic [3:0] a, b,
output logic [3:0] y1, y2, y3, y4, y5);
/* Five different two-input logic
gates acting on 4 bit busses */
assign y1 = a & b; // AND
assign y2 = a | b; // OR
assign y3 = a ^ b; // XOR
assign y4 = ~(a & b); // NAND
assign y5 = ~(a | b); // NOR
endmodule
Correct implementation of conditional operators
/* 4-bit mux; selects one of two 4-bit
inputs d0 or d1
Equivalent to this expression:
If s = 1, then y = d1.
If s = 0, then y = d0.*/
module mux2_4 (input logic [3:0] d0, d1,
input logic s, output logic [3:0] y);
assign y = s ? d1 : d0;
endmodule
Conditional Operators
Syntax: assign [signal operand] = [condition] ? [expression 1] : [expression 2];
If the condition evaluates to TRUE (has a value of 1), the “expression 1” will be assigned to the signal. If the condition evaluates to FALSE (has a value of 0), the “expression 2” will be assigned to the signal.
Reduction Operators
Basically used to ‘demultiplex’ a bunch of signals and perform a logic operation on them at the same time.
Reduction operators imply a multiple-input
gate acting on a single bus
* |, ^, ~&, and ~| reduction operators are
available for OR, XOR, NAND, and NOR
Correct Implementation of Reduction Operators
module and8 (input logic [7:0] a,
output logic y);
assign y = & a;
// &a is much easier to write than
// assign y = a[7] & a[6] & a[5] & a[4]
// & a[3] & a[2] & a[1] & a[0];
endmodule
Correct Implementation of a 32 bit adder in system verilog
/* 32-bit adder */
module adder (a, b, y);
input logic [31:0] a;
input logic [31:0] b;
output logic [31:0] y;
assign y = a + b;
endmodule
Correct way to have nested conditional operators
/* */
module whatami(input logic [3:0] d0, d1, d2, d3,
input logic [1:0] s, output logic [3:0] y);
assign y = s[1] ? (s[0] ? d3 : d2)
: (s[0] ? d1 : d0);
endmodule
“Operator Precedence” in System Verilog
It’s like the “order of operations” in Math
Subtraction in System Verilog
There is no operator for it; just use compliment and addition
“Inexpensive” Operations (in hardware)
“Inexpensive” in this case refers to how much resources (space) you need in the silicon.
AND and NOT do not take up too much are in the hardware
Semi-expensive Operations (in hardware)
Multipliers and Shifters take up a fair amount of area on the silicon
Super Expensive Operations (in hardware)
Division and Modulus are so costly that it may not be synthesizable
How equality comparisons (==) work in System Verilog
(N) is the number of comparisons
Step 1) N 2-input XORs to determine equality of each bit
Step 2) An N-input AND to combine all of the bits
“Relative comparison involves a subtraction”
[Revisit]
Format for declaring constants in System Verilog
“N’Bvalue”
- N is the size in bits
- B is the base, and
- Value gives the value
EXAMPLE: 9’h25 indicates a 9-bit hex number (37 decimal or
000100101 in binary)
*If the base is omitted, the base defaults to decimal
*If the size is not given, the number is assumed to have as many bits as the expression in which it is being
used. (Zeros are automatically padded on the front of the number to bring it up to full size)
Floating Values in System Verilog
Indicated by the letter z
Useful for describing a tristate buffer; its outputfloats when the enable is 0
A bus can be driven by several tristate buffers, exactly one of which should be enabled
Tristate Buffer
A three-state logic variable
The type for a tristate buffer in system verilog
“Tri”. not “logic”
tri v. trireg in System Verilog
- Both are types of net declarations that relate to three-state logic (and the behavior of multi-driver nets).
- Often used when dealing with bus systems or signals that can have more than one driver (including scenarios where a high-impedance (Z) state is possible)
- One driver is active at a time, and the net takes that value; If no drivers are enabled, the tri net floats (z), while the trireg net retains the previous value
Key Differences:
* tri: Goes to high impedance (Z) when not driven.
* trireg: Retains the last driven value (holds the previous state) when not actively driven.
Practical Use:
* tri: Useful for buses where no value should be retained when the driver is disabled.
* trireg: Useful when you need the last value to persist even after the driver stops driving the signal.
Bit swizzling
Refers to the process of rearranging or manipulating the individual bits within a binary word, byte, or larger data structure. It’s often used for optimizing performance, encoding data efficiently, or adjusting data layouts for compatibility between different hardware or software systems
Invalid Logic Levels in System Verilog (also known as an ‘unknown state’)
Indicated by the letter ‘x’
This is often a result of an invalid AND operation
Any AND operation involving a float (z) or an invalid logic value (x)
Flopflops have an initial value of ‘x’
Main aspects of modeling combinational logic
1) Floating Values
2) Invalid Values
3) Bit Swizzling
4) Delays
5) Structural Modeling
Concatenate Operator
Indicated by curly brackets: {}
EXAMPLE: assign y = {c[2:1], {3{d[0]}}, c[0], 3’b101};
- y is a 9-bit vector
- If y were wider than 9 bits, zeros
would be placed in the most
significant bit positions - {3{d[0]}} indicates three copies of d[0]
“Delays” in System Verilog
- Helpful during simulation
- Predict how fast a circuit will work (if you specify meaningful delays)
- Helpful for debugging the cause and effect
- Delays are ignored during synthesis
- Delay of a gate produced by the synthesizer depends on its tpd and tcd specifications
- # symbol is used to indicate the number of units of delay
EXAMPLE:
assign #1 {ab, bb, cb} = ~{a, b, c};
assign #2 n1 = ab & bb & cb;
assign #2 n2 = a & bb & cb;
assign #2 n3 = a & bb & c;
assign #4 y = n1 | n2 | n3;
“tpd” and “tcd” specifications
tpd represents propagation delay
tcd represents contamination delay
Crucial parameters used to evaluate the performance of logic gates, flip-flops, or any combinational logic components. Both values are essential to ensure reliable operation of a digital circuit and help avoid timing violations.
Key Differences:
* tpd (Propagation Delay): The maximum time required for an input change to fully propagate and cause the output to stabilize. This is critical for determining the clock period and maximum speed of a circuit.
* tcd (Contamination Delay): The minimum time it takes for an input change to begin affecting the output. This is important for ensuring hold time violations are avoided, and no glitches occur prematurely at the output.
Practical Use:
1) Timing Analysis:
* Propagation delay (tpd) determines the maximum clock frequency at which a circuit can operate.
* Contamination delay (tcd) is used to check hold time constraints in sequential circuits to prevent premature data changes or glitches.
2) Circuit Design:
* Ensuring that contamination delay doesn’t cause premature transitions or data hazards.
* Balancing the propagation delay to maintain optimal performance without violating timing requirements.
Propagation delay
- Definition: Propagation delay, typically denoted as tpd, is the time it takes for a change at the input of a logic gate to cause a valid change at its output. Specifically, it’s the delay between when an input changes and when the corresponding output stabilizes at the correct value.
- Formula:
tpd=t_out_valid−t_in_change
where
t_in_charge is the time at which the input changes.
t_out_valid is the time when the output stabilizes at a valid level
* Importance: This delay is important in determining the maximum operating frequency of a circuit. It limits how fast data can propagate through a series of gates or between flip-flops.
- Units: Measured in time units (usually nanoseconds, ns, or picoseconds, ps).
Types:
tpLH (Low to High Propagation Delay): The delay from a low (0) to high (1) transition at the output.
tpHL (High to Low Propagation Delay): The delay from a high (1) to low (0) transition at the output.
Contamination Delay
- Definition: Contamination delay, typically denoted as tcd, is the minimum time it takes for a change at the input to propagate to the output, potentially causing the output to start changing. This is the shortest possible time in which an input change may affect the output, even though the output has not fully stabilized yet.
- Formula:
tcd=t_out_begin_change-t_in_change
where:
t_in_change is the time when the input changes.
t_out_begin_change is the time when the output starts to change.
- Importance: The contamination delay is important when evaluating hold time constraints and ensures that data does not propagate too quickly through a circuit and cause timing hazards or glitches at unintended times.
- Units: Measured in time units (usually nanoseconds or picoseconds)
Timescales
Timescales are used to define the time units and time precision for simulation. They play a crucial role in the design and operation of test benches by controlling how delays are interpreted and how time-based operations are simulated
Syntax: `timescale <time_unit> / <time_precision></time_precision></time_unit>
where,
time_unit: Specifies the units of time used for delays and simulation time (e.g., 1ns, 10ps).
time_precision: Specifies the precision or the smallest time step in the simulation (e.g., 1ps, 0.1ns)
Net types
Net types represent physical connections between different modules or components in a hardware design. Nets are used to model the interconnections of hardware elements, particularly where one signal can be driven by multiple sources (such as wires or tri-state buses). Unlike variables (like reg or logic), nets represent electrical connections that can have multiple drivers, and their values are usually determined by the values of the signals driving them.
Key Characteristics of Net Types:
1) Driven by Assignments: Nets represent values driven by multiple sources using continuous assignments (e.g., assign statements or module outputs).
2) No Value Storage: Nets do not store their value; they simply reflect the value driven by their drivers.
3) Multi-Driver Capability: Some nets (like wire or tri) allow multiple drivers, and the simulator resolves the final value based on the logic of the drivers.
“logic” v. “reg”
logic (SystemVerilog Data Type):
Definition: In SystemVerilog, logic is a more flexible, general-purpose data type that can be used to model both combinational and sequential logic.
Usage:
1) logic can be used in both continuous assignments (using assign statements) and procedural blocks (like always blocks). This eliminates the confusion between wire (for combinational logic) and reg (for sequential logic) that existed in Verilog.
2) It is part of the four-state logic system, meaning it can represent values like 0, 1, Z (high-impedance), and X (unknown).
Advantages:
1) Unlike reg, logic can be used in both combinational and sequential logic contexts, making it more versatile.
2) It simplifies code by reducing the need for separate data types like wire and reg to differentiate between different types of assignments.
reg (Verilog Data Type):
Definition: In Verilog, reg is a data type used to represent variables that can hold their value across multiple simulation time steps. It is typically used in procedural blocks like always or initial.
Usage:
1) reg can store a value and is typically used in sequential logic (such as flip-flops) where signals need to be assigned in always blocks using non-blocking assignments (<=).
2) Despite its name, reg does not necessarily correspond to a hardware register. It can represent both combinational and sequential logic in Verilog.
Limitations:
1) Cannot be used with continuous assignments (assign statement). It is restricted to procedural blocks.
2) Single-bit or multi-bit values can be represented, but it doesn’t support the four-state logic system inherent in logic (introduced by SystemVerilog).
read and write busses v. bidirectional bus for memories
