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Electronics Flashcards

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1
Q

How do we deal with noisy signal in electronics

A

We want a shmitt trigger so that when we get a signal we immediately move to another state that’s beyond it so we don’t get a spiky signal just pure positive

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2
Q

What are sources of noise

A

Chemical - temperature, pressure, humidity, light intensity
Instrumental - associated with physical and electronic (eg thermal johnson, flicker, shot etc

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3
Q

What is thermal johnson noise

A

caused by random thermal motion nof charge carriers in electrical circuit

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4
Q

Shot Noise what is

A

quantum noise - the idea that charge and energy quantized -average for constant each individual have their own fluctiation

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5
Q

Flicker noise

A

1/f or pink noise because of its 1/f dependence
usually major noise at lower frequencies
origins unknown - generally most things show flicker noise, diodes, transistors, resistors etc

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6
Q

ENvironemtnal noise

A

things all around us have noise of varying frequency more of course at lower end

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7
Q

Where is the est and worst noise

A

worst at DC - low frequency (no) and best at white noise region

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8
Q

How can we increase S/N generally (2 methods)

A

hardware and software
hardware is grounding and shielding, can remove with electrical filters,
Software - ensemble averaging, digital smoothing etc

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9
Q

What is Lock in amplifier

A

use lock in and phase sensitivie detection to detect signal at specific reference frequency and phase -

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10
Q

GO THROUGH MATH OF LOCK IN (do on own) lecture 16 slide 7 or os

A
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11
Q

How to calculate any number system based on base

A

MSB*Base^m, + next bit Bm-1)
note MSB is most significatn bit - go until least significant bit
note m goes all the way down to 0 so the LSB least significant bit is the bit * B^0

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12
Q

Rules of converting from binary to dec and dec to binary

A

binary to dec - use the 2^ rule
Decimal to binary -
Continuously divide by 2 and the remainders are the digits of your binary numbers.
It goes from LSB to MSB (so the very last number you generate is your MSB (1 and thats when you have 1 divided by 2 (0 R1?)

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13
Q

What is a bit vs a byte vs kB etc (and a word)

A

1 binary digit is a bit, 8 are a byte, and 2^10 is a kilobyte so 1024 Bytes
Megabyte is 2^10 kB or 2^20 bytes so 1048576 B
a single number represented by a group of bits is a word (no fixed size)

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14
Q

What is binary coded decimal?

A

you represent each digit of a decimal number with 4 bits of binary

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15
Q

What is ASCII

A

American Standard Code for Info exchange
alpha numberic code uses 7 bit word to code number letter or command

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16
Q

How to derive boolean expression from truth table

A

Sum of Product or Product of Sums
Sum of Products - look at high states - for inputs multiply them (0 is not, 1 is as is) and sum the terms

For Products of Sums - look at your low states 0
for low states sum the inputs (0 is as is 1 is not) and that makes a term
multiply these terms

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17
Q

Go over basic theorems of logic

A
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18
Q

What does A +A =

A

A

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19
Q

What does A*A =

A

A

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20
Q

What is A+A’

A

1

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21
Q

what is A*A’

A

0

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22
Q

What does A+B*C =

A

(A+B)(A+C)

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23
Q

A*B’+B=

A

A+B

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24
Q

A+A*B

A

A

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25
Q

A*(A+B)=

A

A

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26
Q

(A+B’)*B

A

A*B

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27
Q

What are Demorgans laws

A

(A+B)’ = A’ B’
A’B’ = A’ +B’
The negation (NOT) of a disjunction (OR) is the
conjunction (AND) of the negations.
* The negation of a conjunction is the disjunction
of the negations

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28
Q

What is XOR in boolean

A

A (XOR) B = AB’ + A’B

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29
Q

What is XNOR

A

(A(XOR)B)’

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30
Q

Whats the unverisal gate

A

NAND

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31
Q

[pracitce nand gte to xor

A
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32
Q

How do you build a simple NAND gate in analog

A

inverter with 2 swithc in series to ground - input - means not connected - input 1 - means connected
THe switched wire goes to a node where it is parallel - V out and Vs (resistor)
So basically only goes to ground if 11

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33
Q

Not gate implementation in analog

A

We have a switch to ground - But replace the switch with transistor
so its
V+
resistor
then node in paralle l to vo OUT or to aour transistor to ground
SO
if we have signal on - the transistor conducts and we go to ground - low state
if we are not coducting - the transistor doesnt conduct goes to v0 high state

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34
Q

What is NOR gate analog circuit

A

So this is our not gate
BUT
instead of just a plain voltage input going in
we have 2 inputs A and B in parallel - each has a diode before they join - and they join and go to the base

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35
Q

How do you calculate noise margin

A

High level is VOH - VIH
low level is VIL - VOL

note IH is input high
IL is input Low
OH is output high
OL is output Low

36
Q

What is propogation delay?

A

the time ti takes to swithc or for a transisitor to function
We have rise time and fall time in the circuit
Propogation time is the average of the two swtiching times measured at 50% point (so time from start of switch to 50% point)
TPHL and TPLH

37
Q

What is storage time and what does it effect?

A

so If we have a BJT - not analog circuit
when the transistor conducts - our output voltage is brought down to SATURATION voltage 0.2 (this means the transisitor is saturated (so not all voltage goes to ground I guess - depending on saturation of transistor)

Being saturated however means we have excress charge on the base region (makes sense - once you reach a certain level of base voltage (saturation) you aren’t conducting any extra)
This excess charge at the bease means it TAKES LONGER to turn off the device - this extra time to dissipate charge at the base is called STORAGE TIME
so faster to turn on then turn off

38
Q

How do we decrease storage time? -

A

We use a SHOTTKY DIODE - It prevents saturation of the transistor (thus doesnt take as long to turn off)
it does this by having another wire from the base going to the collector with our SHOTTKY diode on it (so one way) - has a very low voltage drop so shunts the excess current to the collector

39
Q

How can power be dissipated

A

Static - I^2R - passively
Dynamic - I^2R due to charging and disrcharging through resistances

40
Q

What is Power Delay Product

A

the power it takes to turn off and on our logic gate
- performance factor to compare logic families
calculate PDP as
tPD *power dissipation (propogation times power dissipation)

41
Q

Recgonize the following:

A

) Symbol for an inverter operating with power supplies of 0 V and V+.
(b) Simple inverter circuit comprising a load resistor and switch.
(c) Inverter with NMOS transistor switch.
(d) Inverter with BJT switch

42
Q

What are the 3 logic families

A

TTL, CMOS and ECL
TTL is transisitor transistor logic
CMOS is complementary metal oxide semiconductor
ECL is emitter coupled logic
ECL sucks

43
Q

General characteristics of 3 logic families

A

CMOS - low power consumption - using ina ll microcomputer chips (so can put a ton of them together and not so much heat)
can be damaged by static
TTL- most rugged least susceptible to electric damage, COnsumer more power not suitable for battery power
ECL- fast - uses more power and careful wiring

44
Q

How do we make TTL logic gates vs CMOS

A

connect BJTs together to make TTL
we connect NMOS andPMOS to make CMOS

45
Q

What is noise margin?

A

noise immunity is the idea that we can tolerate noise and still have fidelity of 1’s and 0s - an in between signal is properly shunted to 0 or 1
eg 5 - 2.5 is 1 0 - 2.5 is 0

46
Q

How do we improve noise immunity

A

Noise margis are the differences between what we allow our High input value to be vs what the Hihg output is (see the low as well)
so for example can input 2.8 and thats within Input High and will only output between 4.8-5 for output high

47
Q

How is a shottky diode made up and what benefit does it give us

A

its a metal - with a junction then N type silicon
- -very small junction
the voltage drop is very small compared to normal diode because of this 0.25 vs 0.6

48
Q

What is a modern IC PDP (power delay product)

A

10-100 fj

49
Q

What is fan in vs fan out

A

fan in - # of inputs to a gate
fan out is the ability of the output of one gate to drive subsequent gates (eg can the output of this one gate go into 8 other gates after - typically can do 10)

50
Q

Current source vs Sink

A

Current source is one gate driving another - so the I OH (current of output High ) or the current of output low
Similarly Current sink is the opposite - Current of input HIgh or current of input Low - can the incoming current drive our gate

51
Q

How to calculate fan out

A

Ratio of output and input current
min(Ioh/Iih ; Iol/IIl)
note there is a fanout high and a fanout low
overall fan out is whicher is lower

52
Q

3 families of TTL

A

7400 - basic
74S00 - shottky
74LS00 - low power shottkey

53
Q

low power immunity for TTL

A

1-1/6 voltes - tyically operated from 5 V supply

54
Q

INtegration levels

A

Small ,medium ,large -basically how many gates
small is less than 12 medium is 12-100 etc
TTL is used for small and medium - more would be CMOS?

55
Q

How to read IC package name

A

Manufactourer code
specification
Family
Membrer

56
Q

Differnece bteween NOR and NAND Gate
ANALONG circuit

A

NAND has multiple emitter - Nor has 2 separate transisitors

57
Q

What is an open collector

A

If two totem poles are connected - its excessive high current - causes damage so to prevent that remove the active pull up transistor so use an open collector - only acts as current sink - only drive output of low and only work when connected to pull up resistor
ALLOWS FOR WIRED-AND! (allows gates to be connected)
So the idea is our gates are connected to common pull up resistor and any gate can make the signal line low - only output high if all high (AND GATE)

58
Q

N channel vs P channel mosfet

A

For NMOS - source pointing to gaet - for PMOS gate pointing to source
NMOS - turn on with Vgs>0 Gate >0 for Pmos - to turn on with Voltage Less than 0

59
Q

What are complementary pairs

A

in CMOS - use a pair of 1 NMOS and 1 PMOS - and the combined drain is Vout

60
Q

What makes MOSFET circuits great specifically

A

can’t forward bias both of them so cant both draw current
no current consumed at steady state (besides leak)
large noise margin

61
Q

draw CMOS NAND gate

A
62
Q

What are the 2 types of logic circuits

A

COMBINATIONAL (memoryless ) - functions only present values of inputs
SEQUENTIAL - compute output based on inputs and STATE (memory)

63
Q

What are mutlivibrators

A

flip flops 0- basic building blod sequential logic circuits - build up memory

so any circuit with 2 outputs - each that has 2 stable logic level - hi and low
also determined by a clock - clock edge determines when new bit enters

64
Q

What is an SR flipflop -draw - and how does it work

A

essentialy 2 nand gates but the output of each becomes an input for the other
S means set and R means reset (set means output 1 reset means output 0)’output is lathed so SR -FF called gated

Not only change when S or R goes from 1 to 0 not 0 to 1

65
Q

Rules for SR flipflop NAND gate (draw timing diagram)

A

can never be 00,
01 and 10 makes data output
11 is NC - data storage - its a hold because doing from 0 to 1 is not a change
Draw timing diagram
ACTIVELY LOW - when S bar goes to 0 swets a TO 1
wHEN r GOES TO 0 SETS q TO 0

66
Q

sr flipflop WITH nor GATE DESCRIBE

A

active high - so when S set to 1 sets Q to 1 when R set to 1 set q to 0 (activate on leading edge

67
Q

Draw clocked SR flipflop and explain

A

has inputs for clock - so clock needs to be 1 for changes to occur - if 0 no changes occur - others works as normal NAND or NRO sr flip flop
NOTE - S and R here are one step before Sbar and R bar so now for our NAND gate - to switch we need clock enabled - and S to go to 0-> 1 or R- to be 0->1
SO S 1 and clock 1 sets Q to high
and need clock 1 and R 1 to reset it down

68
Q

What is data flipflop - draw

A

Its essentially the clock NAND flipflop BUT instead of two separate R and S inputs - there’s just one Data input - becomes S
and Data -> not -> R
and then Clock with S and R NAND becomes S’ and R’ again
so can make table with this and timing table
so when D on its like S is on
so clock on D on means Q is up
but C on and D down is like R so Q goes down
So called PUSLE TRIGGER - output collows any input change in D as long as c = 1

69
Q

Edge triggered flip flop descobre and draw

A

So this is a data pulse flip flop but instead the not is on the clock
so Data goes in and clock goes into NOT - into first box to make Q
and the output of that has one as is and the other NOT (to make our flipped S and R) goes into another box each output one to one with S and R but the clock now takes initial clock input (not inverted)

So now Q only shifts to high when clock is changing from 0-1 (edge trigger) AND D is 1

70
Q

JK flipflop dsecribe draw

A

So nand gate - J and K - clock goes into both - each output from NAND goes into our NAND flipflop
Key indifference is that our initial NAND actually has 3 inputs and is feedback into by the opposite result at the very end
this allows for all 4 possible combos of J and K

So for Q to change - changes on Clock rising edge 1 and a J of 1 sets it to high and a K of high sets it back down

71
Q

Flip flop application

A

data storage, counters etc

72
Q

WHat are 2 types of counters

A

Ripple (asynchronous) - flip flop output serves as source for triggering other flipflops
Synchronous - all flip flops triggered by same clock signal

73
Q

How are asynchronous vs synchronous counters wired

A

So the output of one flipflock - becomes the clock for another so basically like a ripple
for synchronous all the same clock
Negative edge counter - works as N bit counter - basically as you move down the FF’s they have larger lengths of time they’re on or that they osciallate between on and off

74
Q

How to analyze synchronous counter

A

put counters in arbitrary state determine output
use new input to determine next state
set up next form current

75
Q

) Explain briefly why CMOS
gates are advantageous in terms of power consumption.

A

It is impossible to forward bias both MOSFETs
simultaneously to draw current from the power supply.
* No power is consumed at the steady states (except ~10nW
due to leakage current) regardless of the logic state of input.
* Other advantages include larger noise margin, better
immunity to temperature fluctuation, large fan-out capability

76
Q

Difference between pull up and pull down transistor

A

Pull down acts as current sink - at low output - pulsl voltage down to ground
- so from output its below it and pulls current down
Pull up - acts as current source - when high output - this is the one right above out output and its current sourcing or pull up - send the current down into output

77
Q

What is open colelctor and how is it implemented

A

so its going to be our TTL gate WITHOUT a pull up resistor sso only pull down (only current sink) - which basically means always high unless we are pulling down
this allows for WRIING AND -
So each individual gate does not have a pull up but there is ONE COMMON pullup for all of them
-any collector pulls the line low but the output is high only when they are all high - that’s why its WIRED AND
(conversely wired or is when all connected to a common pull down)

78
Q

For SR Flip flops describe their behaviour

A

Basically when either S or R goes from 1 to 0 they;re behaviour occurs (set or reset) (set making Q 1 and reset making Q 0 -
states can be 1 , 0; 0, 1 or 11 (No change - hold( - can never be 00

OK this makes sense starting with zero because anand gate with a - input HAS to be 1

79
Q

SR flip flop for NOR gate behavioru

A

0 0 is hold, from 0 -1 causes our action 0->1 on S makes Q = 1
never 1 1

80
Q

Clocked SR flipflop

A

So SR NAND gflip flop BUT - have clock at start clock goes into and with S and R and these make S and R prime and we read S and R prime like a normal SR flip flop
(so 11 set not change, 1 0 means reset and 0 1 means set) and no 00

to draw start with clock at 0 the move to 1 then try all the combos of R and S keeping in mind starting with 0 gets you rresults

81
Q

Pulse trigger data flip flop

A

so same idea as clock flip flop but S and R represented by D data - and data makes S and R opposite by nature (one is a not) so can never have a set state - if clock is up - either data state makes a change (set or reset) - called PUSLE trigger

82
Q

List all of the flipflops and draw them

A

SR NAND
SR NOR
Clocked SR NAND
Pulse trigger SR NAND
edge trigger
JK flipflop

83
Q

What happens to JK fliplf op (whats its output

A

so 0 0 - no change
1 0 makes 1
0 1 makes 0

but 11 is toggle as in every clock goes back and forth!! key for writing out the output

84
Q

How to solve counter problem

A

Set counter up abritrarily
set up inputs then do outputs and keep going as counter moves up

85
Q

Draw an N and P mostfet (loabel drain source and gate)

A

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