Electronic- Semiconducting Processing Flashcards
What does semiconductor technology require?
Growth, control and patterning of semiconductor layers of the very highest quality. Relies on having extremely high quality substrates upon which the devices are fabricated. These are semiconductor wafers and are generally single crystals
Range of sizes of wafers
From 61cm diameter for large scale Si device to 5cm for specialist materials
What are wafers cut from?
Larger boules of single crystal semiconductor material
Czochralski growth of boules
A Czochralski puller holds a semiconductor crystal melt in a rotating crucible (boron nitride). A rotating crystal seed is lowered into contact with melt. As seed is pulled up gradually additional crystallisation from melt is observed. Rotations prevent temperature gradients due to convection currents
What is needed for high quality Czochralski growth?
Temperature control using heating and insulation, and rate of pulling critical. Mainly to control shale of crystallisation front which is found above melt line due to surface tension
Shapes of crystallisation front for Czochralski
Ideally convex from crystal so that crystal diameter will increase and dislocations will grow out.
If concave the crystal diameter will decrease and dislocation will grow towards the centre axis
Problem with III-V materials for Czochralski growth
Can have an element with high vapour pressure leading to selective loss and non-stoichiometric melt. To solve, melt has a layer of liquid boron oxide above. This is liquid encapsulated Czochralski growth
How are wafers made from boules?
Boules sown inti wafers (boules aligned using X-ray diffraction before cut). Cut wafers then check-mechanically polished so roughness <1nm. Oxidised during polishing since non-crystalline oxide easier to remove by polishing (fixed thickness). Final oxide layer removed in growth chamber to expose underlying crystal lattice. Polishing platters move in double orbital motion to ensure <20nm flatness over entire wafer
Wafer shape
Circular but with 2 straight edges included. One is long (major flat) which identifies a particular crystallographic direction. One is short (minor flat) which is used to denote doping type of semiconductor
Crystal structures of semiconductors
Si and Ge diamond
Most III-V have zinc blend which is similar to diamond and is effectively 2 tandem fcc lattices for the 2 element groups
What is epitaxial growth?
Grown layers take on crystal arrangement of underlying surface.
Why do semiconductor devices rely on well-ordered single crystal layers?
Reliable electron scattering
Controlled electronic properties
Thus need for epitaxial growth
What does epitaxy of more than one material lead to?
This is heteroepitaxy and involves a mismatch in materials lattice constants. Leads to strain developing which will change the band gaps
Set up for molecular beam epitaxy
Separate effusion cells contain the various materials required for semiconductor growth. Temperature of each cell precisely monitored to achieve correct growth conditions. Shutter on each cell controls introduction of each material. Wafer is in the line of sight of all effusion cells.
Conditions in MBE
System under ultra-high vacuum with pressure <10^-9mbar. Mean free path of atoms from effusion cells is much greater than cell to wafer separation. Wafer heated to a process and material-dependent temperature
Why is heating of wafer controlled in MBE?
It controls the degree of surface mobility of incident atoms. Different growth conditions result from high/low surface mobility. Too high a temperature leads to selective loss of a particular element and a change in material stoichiometry and properties
How do incident atoms ideally add to surface in MBE?
Add to surface one atomic layer at a time
How to monitor growth in MBE
Reflection high energy electron diffraction (RHEED). Uses diffraction of electron beams having 10-30keV energies. Diffracted beams incident on fluorescent screen and detected using CCD camera or photomultiplier. Diffraction pattern gives information about crystal structure.
How to know number of grown atomic layers from RHEED
Any particular diffraction spot oscillates in intensity as each successive layer is formed. Count number of RHEED oscillations over time to know how many atomic layers grown (peak to peak)
Methods of local doping
Ion implantation
Diffusion
Ion implantation
Most common. Ions of dopant element accelerated towards semiconductor substrate. Ion energies 10-500keV. Results in graded dopant profile and controllable sub-surface doping. Higher energy means more dopant ions penetrate deeper. High energy of ion results in damage to semiconductor crystal
Diffusion
Introduce a 100% dopant layer to the surface of a semiconductor region to be doped. Heat treatment promotes diffusion of dopant into semiconductor. Different dopant profiles result from having fixed or unlimited dopant source from the temperature and from anneal time. Multiple doping operations can be used to create alternating electronic character through the device depth
How are patterns made on semiconductor?
Defined using an electron or photo-sensitive resist and irradiating with focussed electrons or light of a suitable wavelength
Patterning by electron-beam lithography
Typical resist PMMA. Deposit resist layer. Write in pattern with electron beam (5-100keV) which breaks the polymer chains and increases solubility. Dissolve plastic regions exposed to electron beam. Deposited final material. Lift off resist in acetone to leave desired structure
Patterning using photolithography
Deposit resist layer expose to extreme ultraviolet radiation through optical mask (smaller features need smaller wavelength). Dissolve resist regions exposed to electron beam. Deposit final material over all. Lift of resist in acetone to leave desired structure e
Etch process for patterning
Deposit material layer (semiconductor) on substrate. Add pattern of resist. Etch away exposed semiconductor with ions/chemicals. Remove resist chemically
