ECE3073 Midsemester Test Flashcards
What is the difference between von Neumann and Harvard architecture?
von Neumann: Address and data bus is shared between memory and instructions.
Harvard: Separate data bus for memory and instructions. More advanced and can read data while executing instructions. It has higher memory bandwidth.
What is the difference between the CISC and RISC architecture?
Complex Instruction Set Computing: CISC supports hundreds to thousands of assembly instructions. Provides a wide range of powerful instructions, and is easy for a human programmer. The hardware to support such a wide range of instructions is slow and complex.
Reduced Instruction Set Computing: Complex instructions are slower than a sequence of simpler operations doing the same thing. Simple, fast computers with many registers and few instructions were developed. High level programming languages can convert complex instructions into smaller assembly instructions for the RISC processor. However, the program size is longer.
What is I/O space and its advantages/disadvantages?
Advantages: Requires less address decoding logic. There is more space for instructions and data in memory space.
Disadvantages: Requires it’s own read and write instructions.
What are the different control and general registers in the NIOS system? What is the program counter and OP-code?
6 control registers (ctl0 to ctl5) &ctl0 is for status. ctl13 is to enable interrupts for certain interrupt levels.
32 general purpose registers (r0 to r31). & r0 is zero register. r1 is the assembler temporary used for pseudo operations. r32 is return address for function calls.
Program counter: 32 bit register containing the address of the next instruction.
Each instruction has an OP-code which is contained in bits 0 to 5.
Name different types of NIOS instructions.
Data transfers, arithmetic, logical and shift/rotate, comparison, branch and jump, subroutine linkage and control instructions.
What are the steps when there is an exception?
Save processor status. Enable supervisor mode. Disable any other external processor inputs. Write address of instruction after exception to r29. Determine the cause of exception.
What is a software trap and what is it used for?
Trap instruction is inside of program. Transfers control to a different program.
What is a hardware interrupt? What are the requirements for a hardware interrupt to occur?
Raised by an external source. Assert irq0 to irq31. Interrupt is generated if ctl0: status bit(0)=1 (PIE bit must be active), interrupt request irqk is asserted, corresponding ienable in ctl3 is enabled.
The exception routine will determine which interrupt has the highest interrupt (by reading the pending interrupts).
What is an unimplemented instruction?
Exception occurs when processor encounters valid instruction that is not implemented in hardware.
What are the encoding types for an I-type and J-type instruction?
I-type: IMM16 is a signed number of bytes offset relative to the current instruction.
J-type: IMM26 is treated as an absolute word address. To convert to 32 bits, two zeros are attached to LSB and 28-31 are copied from current PC.
For a jump to a memory located in memory (jmp rA) then the full 32 bit address in rA is used.
What is synchronisation and when can synchronisation errors occur?
The sender/receiver is fast enough to accept the data as fast as it is required/sent or a clock signal is available to pace the transfer.
Synchronisation is required when data is transferred betwen two systems at different speeds. If a fast computer sends characters to a slow printer, it may send new characters before previous ones have been read.
How does an asynchronous handshake input work?
Provides synchronisation by passing handshake signals between computer and peripheral device.
Input: Computer has a data input and a control bus. Computer and input device signal to each other.
Idle: Interface says “no data available”
Data ready: Interface says “data now available”
Data taken: Computer says “data has been taken”
How does an asynchronous handshake output work?
Output: Computer has data output and control bus. Computer and output device signal to each other in a similar fashion to input.
Idle: Interface says “ready to receive data”
Data ready: Computer says “data now available”
Data taken: Interface says “data has been taken”
What is a polling loop? What is latency?
Processor checks over data from different devices. If data is present, then execute service for that device.
Latency is an important consideration. The time taken between changing the input and the processor responding to it (including the service routine).
To find the maximum latency, make sure to include the first “in” instruction assuming that the sample of the I/O port misses the bit change.
What are the advantages and disadvantages of polling?
Advantages: Responds very quickly for small number of devices. Any amount of devices can be supported. Flexible, I/O can be added/deleted by adjusting the list.
Disadvantages: Consumes computer time when no I/O operations are occurring. Response time is slow for large number of I/O devices. Difficult to do other things whilst polling. Urgent I/O request cannot suspend the servicing of low priority tasks.
What are the advantages and disadvantages of a hardware interrupt?
Advantages: Normal code program can be written without referencing I/O. No I/O operations means no CPU time is used. Multiple levels of interrupt can be used to allocate priorities.
Disadvantages: System hardware is more complex. Fixed time overhead for context switching (from main code to exception code) which limits maximum throughput.
What is a DMA device?
Extra hardware monitors service requests from peripheral devices and takes over data transfer functions of microcomputer. Acts as middle man between peripherals and microprocessor.
Peripheral device signals DMA it needs service. DMA shuts down computer, takes over bus. DMA provides data transfer between peripheral. Computer allowed to regain control of bus.
What is bus interfacing and multi-master bus?
Bus Interfacing: Modern computers connect circuits using a parallel bus system. There may be an address bus, data bus and control bus connecting memory, I/O and other devices.
Multi-master Bus: Bus arranged so that when one master drives the bus, the other master has released the bus.
Characteristics of digital inputs and outputs?
When a computer outputs a digital signal, the data only appears on the bus for a short time. We need to use a flip-flop or similar to hold it’s level.
When a computer is reading a digital signal from outside, there’s a very short timeslot when the input is read. A tri-state buffer allows us to place data on the bus for a very short time.
What is dynamic memory and EPROM?
Dynamic Memory: Stores logic values as a charge on capacitor. Reading involves sensing the resulting charge flowing from a capacitor. Capacitor values must be regenerated regularly to ensure they do not discharge and lose stored information.
EPROM: Large voltages are applied to the transistor gate and electrons flow to the gate. Discharging requires ultraviolet light, allowing electrons to jump past the insulation.
What is asynchronous serial communications? What are start and stop bits, frames, clock accuracy, and parity?
Communications by synchronizing using special signals in the transmission medium. Good for shorter distances.
Start and stop bits: ensure that there is always a high to low transition at start of each frame.
Frame: information is sent down path as sequence of bits organized into a frame. One frame transfers one byte or character, usually with a start bit, parity bit and stop bit.
Clock accuracy: Characters are received correctly if the sampling point is less than a half bit away from the centre of the bit.
Parity: Odd parity: total number of 1’s in data is odd (including parity bit). Even parity: total number of 1’s in data is even (including parity bit). Two errors or even number of errors cannot be detected.
What are the NIOS registers for the UART RS232 interface?
0: rxdata (RO), for RxData [7:0]
1: txdata (WO), for TxData [7:0]
2: status (contains receive char ready, rrdy, used for detecting packet end)
3: control
How does the RS232 standard work?
Logic ‘1’ is indicated by a negative voltage of about -10V and logic ‘0’ signal by a positive voltage of about +10V.
Before data: Serial line is held at logic ‘1’.
Start of data: Start of data frame is signaled with start bit of logic ‘0’.
Data bits: Transmitted from least significant bit to most significant bit.
Finish data: Finished with either one or two stop bits with logic ‘1’.
One and a half stop bits indicate that the UART will transmit 2 stop bits but will receive 1 stop bit.
Baud rate: the reciprocal of the bit time (time taken to send one bit).
What is a framing error? What is a overrun error?
Framing Error: Stop bits of data frame are always logic ‘1’. If the receiving end detects a stop bit as logic ‘0’, then this is a framing error. There could be noise or the baud rates may not match.
Overrun Error: A new frame is received by the receiver but the receiver data buffer has not been read. The new data overrides the previous data.
What is the I2C bus and how does it work?
Popular, low cost method of transferring between multiple masters and slaves. The master provides the clock signal on SCL.
Start signal is 1 to 0 on SDA while SCL is 1 (clock is held high). Stop signal is 0 to 1 on SDA while SCL is 1 (clock is held high). Data bits are transferred on 0 to 1 on SCL.
Clock stretching: If an addressed slave is slow and not ready to receive data, it can slow down the master by holding down the clock signal longer (not ready to transfer more data).
What is the memory cache? What is spatial and temporal coherence?
Memory Cache: Small amount of fast memory that holds copies of some contents of main memory. By relying on spatial coherence and temporal coherence, the cache is arranged to speed up memory access.
Spatial coherence: if the processor accessed a memory location, the chances are it will access an adjacent location soon.
Temporal coherence: if the processor accessed a memory location, it may access the same one again.
What is a cache hit? What is a cache misses and the types of cache misses?
Cache Hit: A cache hit occurs when a computer requests the contents of a particular memory location and the cache contains the information and it can provide it without accessing main memory.
Cache Misses: If memory is not readily available in cache, then the CPU has to copy it to the cache. Compulsory miss: first reference to memory location. It won’t be in the cache if it’s the first time you’ve visited it. Capacity miss: the working set is too big for the cache. Conflict miss: miss that could have been avoided, if the cache had removed something earlier.
What is pipelining?
Without pipelining, only one instruction can be processed by the datapath and the system must wait for the instruction to propagate the full length of the datapath before starting another one. With pipelining, a new instruction can be introduce onto the datapath while a previous one has propagated through the first logic block.
Normally, a processor needs to fetch instruction (IR), register read (RR), execute (E), memory read/write (M), write back result (WB). Pipelining allows another instruction to start executing as an original instruction progresses through its later stages.
What is data stalling and control stalling in the context of pipelining?
Data Stalling: If an instruction is made up of multiple instructions, then the next data is stalled. For example, ldmia is a combination of loading multiple immediate addresses. Therefore the next instruction is stalled until it is fully executed.
Control Stall: If a branch or jump is taken, then the data prepared for the next instructions is removed as it is no longer relevant.
What is an ideal DAC? What are practical errors and issues with analog measurement?
DAC: Ideally, it will take in certain bits, power and voltage reference, then conert it to an analogue voltage ouput or analogue current output.
Practical Errors: Offset error: output voltage shifted up or down. Gain error: amplification of binary input voltage might be incorrect. Random variation: voltage output is scattered around ideal.
Issues with Analog Measurement: Stability: time, temperature, supply voltage affect performance. Settling time: sometimes the output takes time to reach its final value.
How does a ramp up converter work?
Ramp Up Converter: Converts analog signal to digital.
Reset state: clock slowly increases counter. Voltage output from D/A increases. When voltage from D/A is higher than V(in), comparator switches on.
Comparator will set flip flop and stop the clock. The counter output at this point in time is sent to the system.
Conversion time varies depending on how high the input voltage is. Inputting 100mV results in a quicker response time than 10V.
How does a successive approximation converter work?
Turn on MSB of D/A convert while leaving others off.
See if comparator is asserted (voltage in < D/A) then turn off the next MSB and turn on next lower bit.
If the comparator is not asserted (voltage in > D/A) then turn on next LSB. If the comparator is still not asserted (voltage in > D/A). Keep increasing the value on D/A until the voltage in is finally less than the voltage in.
How does a single slope DAC work?
Reset the counter, zero the integration and open the switch.
The counter will slowly increase as the charge builds up in the integrator.
Once the comparator outputs it will stop the clock.
How does a parallel flash converter work?
Take an input voltage and feed it into the resistor network. Each comparator will change depending on the resistor network and voltage input. These outputs form a binary word.
Almost instantaneous.
What are considerations when setting up a sample and hold?
Acquisition Time: Time taken for capacitor to charge until output matches the input.
Aperture Time: When transferred from sample to hold, time diference between time that hold is asserted and location of the point on the input waveform it is held. Typically 100ns.
Voltage References: Zener diodes are most commonly used to provide a reference voltage.
How does a sample and hold circuit in practice work?
The left hand amplifier provides high input impedance for the sample and hold circuit so it does not load the source and a low ouput impedance to charge capacitor C.
The switch connects the analogue input signal to the capacitor and disconnects it during hold period. Hold capacitor maintains the sampled value when switch is open. Right hand unity gain amplifier (follower) provides high input impedance so the capacitor is not discharged.
