ECE3073 Lecture Revision Flashcards

1
Q

What is reentrancy?

A

The ability of a function to be executed concurrently in different processes with the same results. If the code is interrupted at one point, are we able to resume its execution?

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2
Q

What is a process period, initiation rate, initiation time and deadline?

A

Period: interval between process activations. Initiation rate: reciprocal of period. Initiation time: time at which the process must become ready. Deadline: time at which process must finish.

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3
Q

What is a semaphore?

A

An OS primitive for controlling access to critical regions and coordinating multiple processes. We can first get access to a semaphore by pending on it, then perform critical operations, then release the semaphore.

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4
Q

What is a deadlock?

A

One or more processes request resources but never receive the resource. Deadlocks are referred to as a deadly embrace, as one task holds a resource requested by another task that holds a resource requested by the first task.

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5
Q

How do we deal with deadlocks?

A

Acquire resources in the same order. Document the order globally. Wait on semaphores in the same order in all tasks.

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6
Q

What is a mutex?

A

A mutex will raise the priority of a process occupying a resource to the maximum of all processes which are blocked by the resource. This means that the original low priority task can run uninterrupted until it releases the resource.

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7
Q

How do we decide whether to use a semaphore or mutex?

A

Depending on how important the resource is. How quickly we want to release the resource. If we want to release as fast as possible, use a mutex.

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8
Q

What is a data flow graph?

A

A directed graph showing the data dependencies between a number of functions. The basic blocks of a model is a node with one entry point and one exit point. Control Data Flow Graphs implement branches which create multiple paths.

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9
Q

List and describe four optimisation strategies.

A

Expression simplification: constant folding (precompute noncritical calculations), algebraic simplification (factorise algebra into less calculations), strength reduction (replace multiplication or division by powers of 2 by left or right shifts for a less demanding operation). Dead code elimination: sometimes code is entered into a program for the sake of debugging when it will never be run by a user. Remove it! Procedure inlining: eliminate procedure linkage overhead by writing out the interior of a function whenever it is called instead of passing parameters and returns. Loop unrolling: reduce loop overhead and pipeline flushes by writing out multiple iterations of a loop in sequence so that execution requires less branches and control statements.

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10
Q

What are the functions of an assembler?

A

Translate labels into addresses. Handle pseudo-operations. Generate binary for symbolic instructions. Provide a one to one translation of assembly code to machine code.

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11
Q

What is a symbol table?

A

Used by compiler and assembler where each identifier of a source code is associated with information relating to its declaration such as type and location. Find the labels in a source code and convert it to specific addresses stored in the symbol table.

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12
Q

What are testing procedures, controllability and observability?

A

Testing procedures: Provide programs with inputs, execute the program and compare the outputs to expected results. Contrallability: ensure that we can cause a particular internal condition to occur. Observability: ensure we can see the effects of a state from the outside.

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13
Q

What is white-box testing?

A

Testing a program while knowing how the code operates. Test are usually generated from the program structure. Our tests may be more efficient but may not generate all the inputs which a typical user might input. They generally result in path based testing. Control the program to exercise a path, then observe the program to determine if the path was properly executed. May look at whether location on path was reached (control) or whether variable on path was set (data).

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14
Q

What is black box testing?

A

Tests are generated without knowledge of program internals. No care as to how the code actually work, but rather how it works! Select inputs from specifications, determine required outputs. Random: generate random tests, determine appropriate outputs. Regression: tests used in previous version of the system.

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15
Q

How do we evaluate our tests, and what is error injection?

A

Evaluating tests: keep track of bugs found, compare to historical trends. Error injection: add bugs to copy of code, run test on modified code to see if your tests will detect the bug.

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16
Q

What is cyclomatic complexity? What are different path testing strategies?

A

An upper bound to the control complexity of the program. Calculated as M=e-n+2p or M=#decisions+1. Branch testing: Exercise the elements of a conditional, not just one true and one false case. Domain testing: Test cases on the boundaries of inequalities. Test along the boundary as well as on either side. Loop testing: Skip the loop, perform different amounts of iterations, test if the results are as expected.

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17
Q

2006 Q1.1) What is a microprocessor?

A

A computer processor that incorporates the functions of a central processing unit on a single integrated circuit. It is a clock driven and register based circuit that accepts binary input as data and processes instructions stored on memory to produce a digital output.

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18
Q

2006 Q1.3) What is the difference between a microprocessor and a microcontroller?

A

A microprocessor is simple an integrated circuit with a CPU inside of it. It does not have any RAM, ROM or other peripherals on the chip. Microprocessors perform specific tasks based on specific inputs. A microcontroller has memory, IO, storage and peripherals integrated and can be thought of as an “all in one”.

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19
Q

2006 Q1.4) What is the difference between machine code and assembly language?

A

Machine code is binary code that can be executed directly by the CPU. It is a mixture of 1s and 0s and would be completely indiscernable. Assembly code is plain text code which has a 1:1 direct translation to a machine instruction. A compiler is used to convert this assembly code into machine code for the CPU to execute.

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20
Q

2011 Q1.1) Give the name and purpose of four peripheral registers contained in the NIOS UART peripheral.

A

Rxdata: This register is used for the received data through the UART terminals. Txdata: This register is used for the transmitted data through the UART terminals. Status: This register is used to store specific flags providing information about the transmission of data. The status register can detect different types of errors, or when there is an end of a packet encountered. Control: This register is used to enable specific features for the UART terminal such as enabling interrupts for different errors.

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21
Q

2006 Q2.3) What is memory foldover?

A

Memory fold-over is the effect of not decoding a particular address line resulting in some address bits being left as a “don’t care” Suppose we use a 20-bit address and we leave address bit A19 not decoded. If we choose to read and write address 0x00000, 0x00001… it will have the same effect as using addresses 0x80000, 0x80001.

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22
Q

2013 Q2.4) Explain the process of reading and writing data from a single transister memory cell.

A

To write to a memory cell, we place a particular logic ‘0’ or ‘1’ value on the appropriate vertical line known as the bit line. The word line then activates the transistor briefly, allowing the charge on the bit line to flow to the capacitor. To read from a memory cell, we assert a row line known as the word line, making the transistor conductive and allowing the charge stored in the capacitor to flow into the bit line. We then sense the amount of charge flowing in the bit line to determine its value.

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23
Q

2015 Q1.3a) What is the purpose of a direct memory access controller?

A

A direct memory access controller is an extra hardware device which monitors service requests from peripherals. It takes over the role of data transfers with pripherals from the processor. The DMA can transfer between a peripheral device and memory, bypassing the CPU. Without a DMA, all of the data from memory has to pass through the CPU. Each word of data has to be transferred from the disk, through the CPU and individually placed onto memory.

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24
Q

2015 Q1.3b) What event starts a DMA transfer?

A

The peripheral device will signal to the DMA controller that it needs service. The CPU will then initiate the DMA hardware with a memory start address, the amount of data to be transferred, the device to be used and the direction of transfer. The DMA controller will transfer the data and on completion the controller will notify the CPU that it is complete.

25
Q

2015 Q1.3c) Why can a DMA controller perform transfers more quickly than the CPU?

A

DMA controllers are faster as they can perform read and write operations without using CPU cycles. Without a DMA, the CPU needs to read a byte, then write the byte to each location. With a DMA, the work is taken off the CPU and completed directly memory to memory.

26
Q

2010 Q1.4) Demonstrate how and where a cache fits into the memory hierarchy of a typical microprocessor system. Include in your answer a description of how the cache operates and why such a mechanism improves system performance.

A

CPU caching makes use of the sequential and predictable nature of running a program. The slowest part of running a program is accessing the instructions in memory and placing them on a CPU, we can speed up this fetch by placing a small piece of fast RAM between the CPU and main memory. A cache controller sits between the CPU and main memory. When the CPU requests an item from memory, the cache controller will check if the data is already cached (hit). If it has been cached, it will pass it directly to the CPU. If it has not been cache, the cache controller will take the data from the main memory.

27
Q

2013 Q1.2) Name and describe two characteristics of computer memory accesses which allow cache memory to provide an effective speedup for memory accesses.

A

Temporal: when we access one memory location, there is a good chance we will access the same memory locaiton again. This means our cache can speed up future memory accesses. Spatial coherence: when we access a memory location, we will usually access memory locations around that region. This means we can cache around an area which is being executed to speed up memory access.

28
Q

2006 Q1.5) What happens when an interrupt handler executes for too long and the next interrupt occurs before the last call to the interrupt handler has finished?

A

An interrupt service routine will proceed until it is complete without being interrupted itself. Initially when a code runs, the “Global Interrupt Enable” (PIE) bit will be set to allow external interrupts. When an interrupt occurs, the exception handler will clear the PIE bit to disable any additional external processor interrupts. The processor will perform the interrupt service routine, and then reenable the PIE bit after completion.

29
Q

2006 Q3.2) Explain the code required for allowing hardware interrupts. How does a microprocessor distinguish between multiple sources of interrupt?

A

An interrupt is generated when the “Global Interrupt Enable” (PIE) bit in the status register is asserted, when the “interrupt-request input” (irqk) is asserted and when the corresponding “interrupt-enable” bit (ctl3k) is asserted. For example, if we have an interrupt connected to “irq5”, we need to ensure that bit “5” in ctl3k is asserted. When we run through an interrupt service routine, we clear the PIE bit, check the “ipending” register (ctl4) to determine which interrupt is pending. We can mask out the “ipending” register to determine if a specific interrupt occured and then follow a particular service routine based on our own defined priorities of interrupts.

30
Q

P5) In terms of asynchronous serial communications, explain the meaning of parity error, framing error, overrun error and baud rate.

A

Parity error: Occurs when the data bits don’t have odd or even parity. This may indicate that there is an error in the received message caused by excessive noise. Framing error: Stop bits are not high indicating there is a misalignment of transmitted and received data frames. This could be caused by noise being interpreted as a start bit, or by different baud rates between the transmitter and receiver. Overrun error: Occurs when data is lost at the receiver. The receiver may not have enough space in its buffer to receive the additional information. Baud rate: The speed at which information is transferred on a serial link. Calculated as the reciprocal of the bit time.

31
Q

2010 Q4.1.1) What are the wires called in I2C and what are their functions? How are the wires in I2C driven electronically?

A

The two wires are SCK and SDL. SCK is a clock signal, used to regulate the transfer rate of data. SDL is the data signal, used for transmitting a message. The wires are driven using a pull up resistor and connected using open-collector (drain) bus connections. This means that a slave device can pull a bus line to zero (drain) which requires much less power than asserting the bus line.

32
Q

2010 Q4.1.3) Explain how an I2C network arbitrates simultaneous bus accesses.

A

The start condition is that while the SCL line is held high, the slave will pull the data line low to signal it is ready to communicate. If another slave device wants to transmit, it will detect that the data line has already been pulled down, and stop.

33
Q

2011 Q4.1.1) What are the wires called in SPI and what are their functions?

A

SPI has 3 wires and a chip select. The wires are “Master Out Slave In”, “Master In Slave Out” and “Clock”. The master will generate a clock signal on the clock line. On the rising edge of a clock, data will be transmitted from the master to the slave, or from the slave to the master. Either the master will control the MOSI line, or the slave will control the MISO line to transmit data.

34
Q

2014 Q2.6) Describe the main functions of the 8255A circuit.

A

The I8255A circuit is a general purpose input/output circuit. It consists of three 8-bit bidirectional I/O ports which can be configured as per requirements. It has three ports. Port A and B are an 8-bit output latch/buffer and one 8-bit input buffer. Port C can be split into two parts depending on the control mode.

35
Q

2014 Q2.7) List and provide a brief description of the modes of operation of the 8255A circuit.

A

Mode 0: Basic Input/Output - In this mode, Port A and B is used as two 8-bit ports and Port C as two 4-bit ports. Each port can be programmed in either input mode or output mode where outputs are latched and inputs are not latched. Ports do not have interrupt capability. Mode 1: In this mode, Port A and B is used as 8-bit I/O ports. They can be configured as either input or output ports. Each port uses three lines from port C as handshake signals. Inputs and outputs are latched. Mode 2: Strobed Bi-Directional I/O: In this mode, Port A can be configured as the bidirectional port and Port B either in Mode 0 or Mode 1. Port A uses five signals from Port C as handshake signals for data transfer. The remaining three signals from Port C can be used either as simple I/O or as handshake for port B.

36
Q

2012 Q2.2ii) Draw a diagram showing the major components of a practical sample and hold circuit. Explain the function of each of the components in your diagram.

A

A sample and hold circuit will have a capacitor which follows the analogue input voltage until the switch opens. When the switch opens the capacitor will hold the output voltage. The left hand amplifier provides high input impedance so it does not load the source and low output impedance to allow quick charging of the capacitor. The digital controller connects to the analogue input signal during the sample, and disconnects during the hold. The right hand amplifier has high input impedance so that it does not discharge the capacitor, and low output impedance to drive an external load.

37
Q

2012 Q2.3) Explain what aquisition time, aperture time and pedestal error is in the context of sample and hold devices.

A

Acquisition time: the time taken for the capacitor to match the sampled value from the analogue input. This occurs when switched from hold to sample mode. Aperture time: the time taken for the circuit to react when hold is asserted. This occurs when switched from sample to hold mode. Pedestal error: when the digital control changes state, a small amoutn of the control signal is superimposed onto the output.

38
Q

2012 Q2.2i) Explain why the input signal to an analogue to digital converter is sometimes passed through a sample and hold circuit.

A

Analogue measurements come from data which is continuous and can flunctuate very rapidly. Using a sample and hold circuit and regulate the data input to a system. This ensures that while an input is being converted to digital, that it is held at the same value.

39
Q

P7) Explain why the output signal of a digital to analogue converter is sometimes passed through a sample and hold circuit.

A

A digital system can output more than one analogue system using a single DAC if each analogue output uses its own sample and hold circuit. The DAC can then quickly cycle thorugh each sample and hold outputting the voltage for each circuit while the others are held.

40
Q

P7) Describe how a single slope analogue to digital converter operates. Your description should incorporate the equations governing its operation.

A

The counter is first reset, and we discharge the integrating capcitor. We then close the switch connecting -Vref to the integrator and clock pulses are sent to the digital counter. The output of the integrator will slowly increase until it exceeds the analogue input Vin. Once this happens, the output of the comparator changes, stopping the clock pulses. The current value of the counter will be the digital value corresponding to the analogue input Vin.

41
Q

P7) Explain the advantages and disadvantages of the single-slope analogue to digital converter.

A

Advantages: Being an integrating converter, high frequency noise is reduced as it acts like a low pass filter. Disadvantages: The accuracy will depend on the values of Vref, R, C and the precise measurement of time. Precise and stable resistors are expensive and there may be drift in results with temperature and time.

42
Q

2012 Q2.1i) Describe how a dual slope analogue to digital converter operates. Your description should incorporate the equations governing its operation.

A

An integrator with a voltage input is used to generate a linear ramp waveform which is compared with a voltage input. While the ramp is being generated a counter is increased. When a comparator detects that the linear ramp exceeds the voltage input, the counter is stopped and converted to a digital signal. A dual slope converter works in two stages. Firstly, the integrator is connected to the voltage input for a certain amount of time. Then, we connect the integrator to the voltage reference and reset the counter. Then we allow the integrator to ramp back to zero and the counter will stop.

43
Q

2013 Q1.4) Draw a schematic diagram of a parallel (Flash) A/D converter and explain its operation, advantages and disadvantages.

A

A parallel flash converter takes a particular voltage and feeds it into a resistor network. This resistor network will set many comparators at different voltage levels. A voltage input will then be fed into all of these comparators. Depending on which comparators are active and inactive, a different signal will be sent out along the comparator outputs, forming a digital signal. An advantage of parallel flash converters is that they are almost instantaneous. There is very little overhead associated with the comparators updating. However, parallel flash converters require more complex logic to produce a digital output involving gates on the outputs of the comparators.

44
Q

P7) Explain the operation of an inverted R-2R ladder digital to analogue converter and give an equation which relates the output current of the converter to the component values shown in the diagram.

A

A current of I=Vref/R will flow from the voltage reference through the resistor network. At every junction, there will be a total resistance of 2R on each branch, so the current will be split into half, some flowing horizontally and some flowing vertically. The current flowing to S(n-1) is 0.5(Vref/R) and the current flowing to S(n-2) is 0.25(Vref/R). Depending on the whether the switches corresponding to each bit of the digital input are on or off, the current will be grounded or summed up into an amplifier. The more binary bits that are enabled will direct more of the current to the amplifier and less to ground, resulting in a higher output current.

45
Q

P7) List the advantages of the inverted R-2R ladder digital to analogue converter.

A

The inverted R-2R ladder only uses two resistor values and the DAC draws a constant current from the reference source Vref.

46
Q

2015 Q2.1) In general terms, explain how pipelining can be used to improve the throughput of a computer.

A

Pipelining improves performance by increasing throughput as opposed to decreasing execution time of each individual transaction. An instruction may have 5 distinct activities: instruction fetch, instruciton decode, execution, memory read/write, result writeback. When we use pipelining, we overlap our execution of an instruction. Without pipelining, only one instruction can be processed by the datapath and the system must wait until the instruction propagates thee entire datapath berfore starting on the next instruction. With pipelining, a new instruction can be introduced into the datapath after the previous instruction has propagated through the first logic block and the result latched into the register between the first and second logic blocks.

47
Q

2015 Q2.4a) What is a data stall? What is a control stall?

A

Data stall: Certain instructions require more than one read or write from a register. Therefore, when many instructions are waiting in the pipeline, we may need to stall future instructions to allow an executing instruction to read all the required data. Control Stall: When a branch instruction is taken, often the instructions immediately after the branch instruction may be loaded into the pipeline. If the branch is taken, then those instructions need to be removed.

48
Q

2011 Q3.1) Explain the ready, waiting and running states for a task in a MICRO OS real time operating system.

A

Task Dormant: A task that resides in program space, but has not been made available to MICRO OS. It has been defined in code but not created. Task Ready: Ready to run but not running as another task of higher priority is already running. Task Running: The CPU is executing a task. The highest priority task is placed in this state. Only one task can be running at any given time and a ready task will not run until higher priority tasks are waiting or deleted. Task Waiting: A task can be delayed for a certain amount of time or may be calling on a semaphore or mutex, causing the task to be blocked. This forces an immediate context switch to the next highest priority task.

49
Q

2011 Q3.2) MICRO OS contains a 32 bit counter which increments once at each clock tick. Explain how this counter can be used to measure performance of the system with respect to an individual task. Assume the period of the tick is fixed.

A

Firstly, we can create a task with the lowest priority of all tasks to run the 32 bit counter. We can run the 32 bit counter with no other tasks running to determine the maximum value of this counter (CPU idle). We can then run other tasks with the counter in the background, and measure the final value of the counter. This amount will help us to determine how long the CPU is idle.

50
Q

2012 Q3.3) Explain how the MICRO OS measures the utilisation of a CPU when multiple tasks are running.

A

The idle task increments an integer called OSIdleCtr. OSStatInit() measures the OSIdleCtr over a period of 1 second and this is called OSIdleCtrMax. It is the maximum since no other tasks can consume CPU cycles when the idle task is running during that second. While all other tasks are running, a 2nd lowest priority task called the statistics task records the OSIdleCtr every second and calculates the utilisation. It then resets OSIdleCtr to 0 and sleeps for another second.

51
Q

2015 Q3.2b) Explain what priority inversion is. How can it be fixed?

A

Priority inversion is a scenario in scheduling where a higher priority task is preempted by a lower priority task. This may lead to a system error if the high priority task is starved of its resources. This may also lead to reduced perceived performance of a system. Priority inversion may be preventing a more useful and crucial task from running while a lower one runs. For example, assume a low priority task waits on SemA and takes the resource. Before this task can post SemA again, a medium priority task wakes up and starts executing. A high priority task may wake up and be pending on SemA, and be blocked. But then the medium priority task may wake up and block the low priority task from releasing SemA. The high priority task is effectively blocke due to a low priority task holding the resource and not able to complete. This issue can be solved using a mutex. This is similar to a semaphore, but when a task pends on a mutex, its priority will be automatically raised to a higher priority so it can be executed and release the resource as soon as possible.

52
Q

Extra) What is the difference between “cooperative” and “preemptive” scheduling algorithms?

A

Cooperative: Once started, a task within a cooperative scheduling system will continue to run until it chooses to relinquish control. Preemptive: Tasks can be forcibly suspended if a task with higher priority needs to run based on a system clock or external event. There is additional overhead involved with interrupts.

53
Q

Extra) Explain the features, advantages and disadvantages of RMS and EDFS.

A

Rate Monotonic Scheduling is a preemptive scheduling algorithm. It is used when processes are periodic, require the same amount of CPU time each burst, and when processes are independent. It allocates processes with the shortest period the highest priority. Earliest Deadline First (EDF) scheduling will allocate processes with the earliest deadline the highest priority. EDF can schedule up to 100% of the CPU time while meeting deadlines.

54
Q

Extra) How can we determine whether an RMS scheduler can guarantee that all tasks will meet deadlines?

A

An RMS scheduler can guaranteed meet deadlines for ‘m’ processes as long as the utilisation of the CPU follows the formula: U

55
Q

2009 Q3.1) Describe two methods employed by a compiler for passing parameters to a C function. What are the benefits and limitations of each method?

A

Procedure linkage: When a function is called, the parameters and returns will be placed on a stack. The processor will then branch to the subroutine to complete the necessary task, then branch back out. Procedure linkage is slow due to the stack overhead, but uses less lines of code. Procedure inlining: The code inside of a function is placed in line within the main code whenever the function is called. This means that the overhead associated with passing parameters and returns is eliminated. Procedure inlining is faster, but takes up more lines of code.

56
Q

Extra) What is the difference between a stack pointer and a frame pointer?

A

A stack pointer points to the top of a stack. As you allocate space on the stack, the stack pointer moves to the next point in free memory for pushing and popping new variables. The frame pointer points to the start of the stack frame and does not move during the duration of a subroutine call. Frames are used to set up the portion of the stack that will be used in a function.

57
Q

2009 Q3.3) Explain what is meant by the compiler optimisation technique of “loop unrolling”.

A

A loop will run a particular section of code multiple times until a particular condition is met. However, this requires many branches and has a higher overhead due to pipeline flushes. Loop unrolling aims to serve multiple iterations of a loop with less branches, less control instructions and loop test instructions. Advantages: Increases program efficiency, reduces loop overhead and if the statement in a loop are not dependent on each other, they can be executed in parallel. Disadvantages: Increaes program code size and the possibility of increased register use for a single iteration.

58
Q

Extra) Draw the start, stop, acknowledge, not acknowledge, and data bits used in an I2C transmission.

A