Digital Electronics Flashcards
1
Q
Analogue signals take…
A
Continuous values
2
Q
Digital signals take…
A
Restricted rages of amplitude
3
Q
Binary signals are ____ signals that take only _ ____
A
Binary signlas are digital signlas that take only 2 ranges
4
Q
What does an anolog and digital signal graph look like?
A
5
Q
Why digital?
A
Reliability
- Anologue circuits are more vulnerable to noise
- Digital circuits can tolerate some levels of noise
6
Q
Base 2 means?
A
We can only use 0 and 1
7
Q
How would you write 11010.1 in binary?
A
8
Q
How do you convet decimal to binary?
A
9
Q
The hexadecimal number system represents…
A
A larger range of values with one digit
10
Q
Basic Boolean operations are…
A
AND, OR and NOT
11
Q
If the variable doesn’t have the value 0, it must have…
A
The value 1 and vice versa
12
Q
Symbols like ____ to represent Boolean ____
A
Symbols like A, B etc to represent Boolean variables
13
Q
What do truth tables do?
A
Describe how a logic circuit (gate) outputs depend on it’s inputs
14
Q
What sign is commenly used to represent an Or gate?
A
The plus sign (+)
15
Q
What does an Or gate look like?
A
16
Q
What gate produces an output of 1 whenever when all of the inputs are 1?
A
An Or gate
17
Q
What does an And gate look like?
A
18
Q
What is the Boolean expression for an Or gate?
A
z = x + y
19
Q
What is the Boolean expression for an And gate?
A
z = x . y
20
Q
What sign is used to commonly represent the And gate?
A
The period (dot) sign .
21
Q
What gate produces an output of 1 only when all of the inputs are 1
A
An And gate
22
Q
What is the symbol for a Not gate?
A
23
Q
What is the Boolean expression for a Not gate?
A
z = ¬x
24
Q
What sign is commonly used to represent a Not gate?
A
The ¬ sign is commonly used to represent not. Sometimes a bar over the variable is used also
25
A **Not** gate is a...?
Circuite that inversts - or negates - the input signal
26
What gate produces an output of 1 whenever the input is 0, and an ouput of 0 when the input is 1
A **Not** gate
27
What is the symbol for a **Nand** gate?
28
What is the Boolean expression for a **Nand** gate?
z = ¬ ( x . y )
Sometimes you will see this written in the notation that has a bar over the top
29
What gate produces an output of 1 only when any one of the inputs are 0?
A **Nand** gate
30
A **Nand** gate is...
the logical not of the output of an **And** gate
31
What is the symbol of a **Nor** gate?
32
What is the Boolean expression of a **Nor** gate?
z = ¬ ( x + y )
33
What gate has an output of 0 whenever any of the inputs are 1?
A **Nor** gate
34
A **Nor** gate is...
The logical not of the output of an Or gate
35
What is the symbol for an **Xor** gate?
36
What is the Boolean expression for an **Xor** gate?
37
**Xor** (\_\_\_\_) gate
(Exclusive **Or**) gate
38
Define Commutative laws
Talk about variabls interchanging
39
Define Associative laws
Talk about bracketing variable groups
40
Define Absorption laws
talk about variables absorbing others
41
Define Distributive laws
talk about multiplying through groups
42
Boolean products are ____ functions e.g....
**AND** functions e.g. **A. ~B.C**
43
Boolean sums are ____ functions e.g....
**OR** functions e.g. **A+~B+C**
44
Why are Minterms products?
Becuase they are the logical **AND** of a set of variables
45
Why are **Maxterms** sums?
Becuase they are the logical **OR** of a set of variables
46
What is a Karnaugh Map?
A diagram consisting of a rectangular array of squares each representing a different combination of the variables of a Boolean function
47
What is looping?
Grouping squares in the map that contain 1
48
You loop pairs that are...?
Above or beside each other
49
K-maps reduce the...?
...cost of logic synthesis
50
What cannot be define by a Boolean expression?
Incomplete specified functions
51
What are "Don't care" terms and what are they represented by?
Terms of functions that we don't care about, corresponds to lines in the truth table where we don't specify the output, represented by x
52
Define **propagation delay**
A small time it takes to change state when the inputs change
53
What are the two types of hazards in **gate propagation delays?**
**Static Hazard** and **Dynamic Hazard**
54
Define **static hazard**
When the output undergoes a momentary transition when it is supposed to remain unchanged
55
Define **dynamic hazard**
When the output changes more than once when it is supposed to change only once
56
What do **static and dynamic hazards** look like?
57
When are hazards a problem?
Hazards are always a problem if they occur in logic providing the input to a system with memory
58
**Nand** and **Nor** are common because...?
* They are simpler to build
* They are "logically complete"
59
When is a set of circuit gates logically complete?
A set of circuit gates is said to be logically complete if any boolean function representable by a truth table can be implemented using gates from only that set
60
Logically complete sets include...
* Sets containing AND, OR, INVERTER gates
* Sets containing only NAND gates
* Sets containing only NOR gates
61
How do you implement circuits in **NAND**?
* First obtain the function in simplest sums of products form
* Invert the function twice (this leaves it unchanged)
* Use de Morgans theorem on the lower inversion
* The function can now be implemented using only NAND gates
62
**NAND** is negation of...?
**AND**
63
What is the condition for **static hazard?**
If two groups of 1’s on the K-map are adjacent and non-overlapping (horizontally or vertically) then changing a single input variable can move out of one group into another
64
How do you elimate a **static hazard?**
By including extra groups that overlap the offending transitions
* This adds in circuitry to protect the hazard
65
What are combinational circuits?
Combinational circuits cannot remember a previous output value when an input value changes
66
What are sequential circuits?
Sequential ciruits take into account (or remember) their previous state
67
How is a sequential circuit synchronized?
By a clock signal that consists of periodic 1 pulses
68
What does **SoP** stand for
Sums of products
69
What does **SR Flip-flop** stand for?
Set/Reset Flip-slop
70
What does a **SR Flip-flop** consist of?
Two **NOR** gates
71
What happens when the **S** and the **R** are low?
The **NOR** gates act as inverters for the other input signal
72
What happens when **S** becomes high and **R** is low?
¬Q is forced low and Q is high (set)
73
When **S** returns low after being high in an **SR Flip-flop,** Q...?
Remins high (it is in the set state)
74
What happens when **R** becomes high and **S** is low?
**Q** is forced low
75
When **R** returns low after being high, what happens to **Q?**
Q remains low (the reset state)
76
Are **R and S** normally allowd to be high at the same time?
No, so with **R and S** low, the flip-flop remembers whihch input was high most recently
77
What can we achieve with a **D** type flip-flop?
Setsome data and stores it
78
What is the cost of the function directly related too when it is synthesised using AND and OR?
The
* Number of gates
* Gate inputes
79
A minimum SoP expression is one which has...?
* A minimum number of gates
* A minimum number of gate inputs
80
Why is it helpful to represent K-maps in text form?
* Helpful if we consider larger and larger maps, of more than 4 terms
* And the underlying princioples that we are representing graphically
81
How do you represent a K-map?
By simply recording the decimal equivalent of the high outputs
82
When is a product an implicant?
When any 1, or group of 1’s that may be combined represent a product term
83
When is an implicant prime?
An implicant is prime if it cannot be combined with another term to eliminate a variable
* A single 1 is prime if it is not adjacent to any other 1
* Two adjacent 1’s are prime if they are not contained in a group of 4
* Four adjacent 1’s are prime if they are not contained in a group of 8
* …etc…
84
When can a SoP term not be minimal and why?
When it is containing a term which is not prime because if a non prime term is present the expression maybe further simplified
85
In order to minimise...
we must find the minimal number of prime implicants needed to cover all 1s on a map
86
A minimal solution...
Must include all essential prime implicants
87
How do you find the minimal SoP expression?
* First loop all essential prime implicants
* For simple maps, this can be done by inspection
* For maps of 5 variables or more, it needs a systematic approach – this is where our ∑ notation is useful
88
89
Define a **static hazard**
A circuit contains a **static hazard** where, when one input variable changes, the output may change more than once
90
How is it possible to **overcome** **static hazards**?
By **linking** the **adjacent** **groups** to an **additional** **group**
