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Server Architecture > Definitions > Flashcards

Definitions Flashcards

1
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RP

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PVG

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OSPM

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3
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NVDIMM

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SoC

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PPOG

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PCH

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7
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UPI

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8
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SPC

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8
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UART

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9
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QPI

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9
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DPS

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10
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DIMM

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10
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SR

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11
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DR

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12
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MT/S

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13
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TDP

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14
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AP/SP

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14
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SNC

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15
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DC-SCM

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16
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L1

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L3

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17
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UMA

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17
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NUMA

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18
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L0

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19
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SBSP

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19
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L2

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20
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LEPs

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21
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PLD

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22
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BKC

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23
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FSP

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23
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AGESA

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23
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PBSP

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24
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EC

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24
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vBIOS

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25
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ME

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26
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IEH

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27
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SCI

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28
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HEST

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29
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APEI

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30
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WHEA

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31
Q

CMCI

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31
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EMCA

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32
Q

ASIC

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32
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PPR

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32
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GDDR

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33
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FPGA

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33
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PCU

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34
Q

NMI

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35
Q

DCB

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35
Q

S3M

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35
Q

PFR

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36
Q

DC-MHS

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36
Q

IBL

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37
Q

GbE

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38
Q

DMI

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39
Q

PRoT

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40
Q

SBI

A
40
Q

FRP

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40
Q

EDSFF

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41
Q

MRC

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42
Q

IPMI

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43
Q

GPE

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43
Q

SCI

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44
Q

IRQ

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45
Q

SDSi

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45
Q

TDX

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46
Q

BTG

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46
Q

FIT

A
46
Q

SPDM

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47
Q

ACM

A
48
Q

TME-MT

A
48
Q

TME

A
49
Q

SGX

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50
Q

MKTME

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50
Q

SEAAM

A
50
Q

SEAMRR

A
51
Q

ACTM

A
52
Q

TDVF

A
53
Q

VMM

A
54
Q

I2C

A
55
Q

ASD

A
55
Q

PECI

A
56
Q

I3C

A
57
Q

SPS

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58
Q

BASD

A
58
Q

MCTP

A
58
Q

PMT

A
58
Q

BAFI

A
58
Q

ACD

A
59
Q

CHA

A
60
Q

MC

A
61
Q

LLC

A
62
Q

M2M

A
63
Q

2LM

A
64
Q

B2CMI

A
65
Q

SNC

A
66
Q

CPLD

A
66
Q

CSME

A
67
Q

DICE

A
68
Q

MBIST

A
69
Q

LBIST

A
70
Q

CoT

A
71
Q

SIO

A
72
Q

APU

A
73
Q

NIC

A
74
Q

IaaS

A
75
Q

RTU

A
76
Q

HMAC

A
77
Q

AKC

A

Authentication Key Certificate
-a key written to internal NVRAM that is used to authenticate a capability-specific activation payload, retrieve by sending an IOCTL HMAC

78
Q

CAP

A

Capability Activation Payload
-a token authenticated using AKC and applied to the CPU configuration to activate a new feature, done by sending an IOCTL HMAC

79
Q

QAT

A
80
Q

DLB

A
81
Q

DSA

A
82
Q

IAX

A
83
Q

NPEM

A
84
Q

NTB

A

A device that forwards PCIe traffic between busses like a bridge. Two main purposes: to allow inter-processor communication between different hosts, and to ensure address domain isolation. Non-transparent: one host cannot enumerate or access directly other host PCIe hierarchy, host on side of the bridge will not have visibility to complete memory I/O space on the other side.

85
Q

RCiEP

A

Embedded endpoint that is implemented on the root complex internal logic. Contains the root port and is used to declare the Root Complex Integrated Endpoints support by the Root Complex Event Collector on the same logical bus on which the Root Complex Event Collector is located.

86
Q

RCEC

A

PCIe device that is responsible for collecting and logging error messages from PCIe devices. Part of the PCIe Advanced Error Reporting (AER) feature set, implemented as part of the root complex(PCIe device that connects the CPU to the PCIe fabric). Detects uncorrectable errors, correctable errors, and fatal errors.

87
Q

DVSEC

A

A register locator that acts as a link to access memory-mapped registers. It is available in the configuration space of a device and is used to define a vendor-specific extended capabilities that is not tired to the vendor ID of the component.

88
Q

SRAT

A

Provides the boot time description of the processor and memory ranges belonging to a system locality.

89
Q

HMAT

A

Describes memory attributes, such as memory side cache attributes and bandwidth and latency details, related to Memory Proximity Domains. The OS uses this to optimize the system memory configuration.

90
Q

CDAT

A

Describes performance characteristics of a CXL device or a DXL switch.

Server Architecture (2 decks)

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