Acronyms Flashcards
RP
Reference Platform
SoC
System on Chip
OSPM
Operating System-directed configuration and Power Management
PVG
Platform Validation Guide
PPOG
Power Performance Optimization Guide
PCH
Platform Controller Hub
UPI
Ultra Path Interconnect
QPI
Quick Path Interconnect
SPC
Slots per Channel
DIMM
Dual In-Line Memory Modules
SR
Single-rank
DR
Dual-rank
MT/s
Megatransfers per second
UART
Universal Asynchronous Receiver-Transmitter
DPS
Distributed Power Solid State Drive
DC-SCM
Datacenter Source Control Module
AP
Advanced Performance
SP
Scalable Performance
UMA
Uniform Memory Access
NUMA
Non-Uniform Memory Access
L0
Fully active state
L1
Low-power state, key potions turned off
L2
Low-power sleep state (identical to L3 but power still exists)
L3
Off state
LEP
Link Exchang Parameters
PLD
Programmable Logic Device
SBSP
System Bootstrap Processor
PBSP
Synchronization Up Platform Bootstrap Processor
AGESA
AMD Generic Encapsulated Software Architecture
FSP
Firmware Support Package
EC
Embedded Controller
vBIOS
Video BIOS
ME
Management Engine
BKC
Best Known Configuration
IEH
Integrated Error Handler
WHEA
Windows Hardware Error Architecture
APEI
ACPI Platform Error Interface
HEST
Hardware Error Source Table
SCI
Small Computer Interface
CMCI
Corrected Machine Check Interrupt
EMCA
Error-Correcting Memory Controller Hub Agent
PPR
Post Package Repair
ASIC
Application-Specific Integrated Circuit
GDDR
Graphics Double Data Rate
FPGD
Field-Programmable Gate Array