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CS61 > Datapaths > Flashcards

Datapaths Flashcards

1
Q

RTN(s) for the TRAP instruction

A

R7 ⇐ PC; PC ⇐ Mem[ ZEXT(IR[7:0]) ]

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2
Q

RTN(s) for the JMP instruction

A

PC ⇐ BaseR

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3
Q

RTN(s) for the ADD instruction - register mode -

A

DR ⇐ SR1 + SR2

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4
Q

RTN(s) for the ADD instruction - immediate mode -

A

DR ⇐ SR1 + SEXT(IR[4:0])

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5
Q

RTN(s) for the AND instruction - register mode -

A

DR ⇐ SR1 . SR2

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6
Q

RTN(s) for the AND instruction - immediate mode -

A

DR ⇐ SR1 . SEXT(IR[4:0])

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7
Q

RTN(s) for the JSR instruction

A

R7⇐PC; PC ⇐ PC + SEXT(IR[10:0])

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8
Q

RTN(s) for the NOT instruction

A

DR ⇐ (SR1’)

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9
Q

RTN(s) for the ST instruction

A

Mem[ PC + SEXT(IR[8:0]) ] ⇐ SR

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10
Q

RTN(s) for the LD instruction

A

DR ⇐ Mem[ PC + SEXT(IR[8:0]) ]

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11
Q

RTN(s) for the LDR instruction

A

DR ⇐ Mem[ IR[8:6] + SEXT(IR[5:0]) ]

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12
Q

RTN(s) for the LEA instruction

A

DR ⇐ PC + SEXT(IR[8:0])

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13
Q

RTN(s) for the STI instruction

A

Mem[ Mem[ PC + SEXT(IR[8:0]) ] ] ⇐ SR

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14
Q

RTN(s) for the BR instruction

A

PC ⇐ PC + SEXT(IR[8:0]) iff (N.n + Z.z + P.p)

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15
Q

RTN(s) for the STR instruction

A

Mem[ IR[8:6] + SEXT(IR[5:0]) ] ⇐ SR

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16
Q

RTN(s) for the JSRR instruction

A

R7 ⇐ PC; PC ⇐ (BaseR)

17
Q

Control Instructions for BR

A
  1. ADDR1MUX selects PC
  2. ADDR2MUX selects SEXT(IR[8:0])
  3. PCMUX selects ADDR ADD
  4. LD.PC iff (N.n + Z.z + P.p)
18
Q

Control Instructions for JSRR

A
  1. GatePC
  2. DRMUX selects [111]
  3. LD.REG
  4. SR1MUX selects IR[8:6] ​
  5. ADDR1MUX selects SR1OUT
  6. ADDR2MUX selects 0
  7. PCMUX selects ADDR ADD
  8. LD.PC
19
Q

Control Instructions for TRAP

A
  1. GatePC
  2. DRMUX selects [111]
  3. LD.REG
  4. MARMUX selects ZEXT(IR[7:0)
  5. Gate.MARMUX
  6. LD.MAR
  7. MEM.EN/R
    a. Wait for R
  8. MDRMUX selects MEM.​
  9. LD.MDR
  10. Gate.MDR​
  11. PCMUX selects bus.
  12. LD.PC
20
Q

Control Instructions for LDR

A
  1. SR1MUX selects IR[8:6]
  2. ADDR1MUX selects SR1OUT
  3. ADDR2MUX selects SEXT(IR[5:0])
  4. MARMUX selects ADDR ADD
  5. Gate.MARMUX
  6. LD.MAR
  7. MEM.EN/R
    a. Wait for R
  8. MDRMUX selects Memory
  9. LD.MDR
  10. Gate.MDR ​
  11. DRMUX selects IR[11:9] ​
  12. LD.REG
21
Q

Control Instructions for ST

A
  1. ADDR1MUX selects PC
  2. ADDR2MUX select SEXT(IR[8:0])
  3. MARMUX selects ADDR ADD
  4. Gate.MARMUX
  5. LD.MAR
  6. SR1MUX selects IR[11:9]
  7. ALUK selects Pass Through
  8. Gate.ALU
  9. MDRMUX selects bus ​
  10. LD.MDR
  11. MEM.EN/W
22
Q

Control Instructions for STI

A
  1. ADDR1MUX selects PC
  2. ADDR2MUX selects SEXT(IR[8:0])
  3. MARMUX selects ADDR ADD
  4. Gate.MARMUX
  5. LD.MAR
  6. MEM.EN/R
    a. Wait for R
  7. MDRMUX selects Memory
  8. LD.MDR
  9. Gate.MDR
  10. LD.MAR
  11. SR1MUX selects IR[11:9]
  12. ALUK selects Pass Through
  13. Gate.ALU
  14. MDRMUX selects Bus
  15. LD.MDR
  16. MEM.EN/W
23
Q

Control Instructions for STR

A
  1. SR1MUX selects IR[8:6]
  2. ADDR1MUX selects SR1OUT
  3. ADDR2MUX selects SEXT(IR[5:0])
  4. MARMUX selects ADDR ADD
  5. Gate.MARMUX
  6. LD.MAR
  7. SR1MUX selects IR[11:9]
  8. ALUK selects Pass Through
  9. Gate.ALU
  10. MDRMUX selects Bus
  11. LD.MDR
  12. MEM.EN/W
24
Q

Control Instructions for JMP/RET

A
  1. SR1MUX selects IR[8:6]
  2. ADDR1MUX selects SR1OUT
  3. ADDR2MUX selects 0
  4. PCMUX selects ADDR ADD
  5. LD.PC
25
Q

Control Instructions for JSR

A
  1. GatePC
  2. DRMUX selects [111] ​
  3. LD.REG
  4. ADDR1MUX selects PC
  5. ADDR2MUX selects SEXT(IR[10:0])
  6. PCMUX selects ADDR ADD
  7. LD.PC
26
Q

Control Instructions for JSRR

A
  1. GatePC
  2. DRMUX selects [111] ​
  3. LD.REG
  4. SR1MUX selects IR[8:6] ​(not shown in the simplified datapath)
  5. ADDR1MUX selects SR1OUT
  6. ADDR2MUX selects 0
  7. PCMUX selects ADDR ADD
  8. LD.PC
27
Q

Control Instructions for TRAP

A
  1. GatePC
  2. DRMUX selects [111] ​
  3. LD.REG
  4. MARMUX selects ZEXT(IR[7:0)
  5. Gate.MARMUX
  6. LD.MAR
  7. MEM.EN/R
    a. Wait for R
  8. MDRMUX selects MEM.​
  9. LD.MDR
  10. Gate.MDR​
  11. PCMUX selects bus.
  12. LD.PC
28
Q

Control Instructions for ADD (register mode)

A
  1. SR1MUX selects IR[8:6]
  2. SR2MUX selects SR2OUT
  3. ALUK selects ADD
  4. GateALU
  5. DRMUX selects IR[11:9]
  6. LD.REG
29
Q

Control Instructions for ADD (immediate mode)

A
  1. SR1MUX selects IR[8:6]
  2. SR2MUX selects SEXT(IR[4:0])
  3. ALUK selects ADD
  4. GateALU
  5. DRMUX selects IR[11:9]
  6. LD.REG
30
Q

Control Instructions for AND (register mode)

A
  1. SR1MUX selects IR[8:6]
  2. SR2MUX selects SR2OUT
  3. ALUK selects AND
  4. Gate.ALU
  5. DRMUX selects IR[11:9]
  6. LD.REG
31
Q

Control Instructions for NOT

A
  1. SR1MUX selects IR[8:6] ​
  2. ALUK selects NOT
  3. Gate.ALU
  4. DRMUX selects IR[11:9]
  5. LD.REG
32
Q

Control Instructions for LEA

A
  1. ADDR1MUX selects PC
  2. ADDR2MUX selects IR[8:0]
  3. MARMUX selects ADDR ADD
  4. Gate.MARMUX
  5. DRMUX selects IR[11:9]
  6. LD.REG
33
Q

Control Instructions for LD

A
  1. ADDR1MUX selects PC
  2. ADDR2MUX selects SEXT(IR[8:0])
  3. MARMUX selects ADDR ADD
  4. Gate.MARMUX
  5. LD.MAR
  6. MEM.EN/R
    a. Wait for R
  7. MDRMUX selects Memory
  8. LD.MDR
  9. Gate.MDR
  10. DRMUX selects IR[11:9]
  11. LD.REG
34
Q

Control Instructions for LDI

A
  1. ADDR1MUX selects PC
  2. ADDR2MUX selects SEXT(IR[8:0])
  3. MARMUX selects ADDR ADD
  4. Gate.MARMUX
  5. LD.MAR
  6. MEM.EN/R
    a. Wait for R
  7. MDRMUX selects Memory
  8. LD.MDR
  9. Gate.MDR
  10. LD.MAR
  11. MEM.EN/R
    a. Wait for R
  12. MDRMUX selects Memory
  13. LD.MDR
  14. Gate.MDR
  15. DRMUX selects IR[11:9]
  16. LD.REG

CS61 (9 decks)

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