CSO1 DIGITAL LOGIC Flashcards
MULTIPLEXERS
-i/o
-n control inputs (control bits)
-2^n data inputs (2^n combinations of n and ~n signals)
-1 output
control inputs choose the output with AND gates
if control signals are all 1 input is propagated
if 0 ,0 is propagated
MULTIPLEXERS
-gate structure
data input0 ————->[AND gate] ——–> [OR gate]—–>[output]
data input1 -^———->[AND gate] —————^
xxxxxxxxxxx| xxx^
xxxxxxxxxxx| [NOT gate]
xxxxxxxxxxx|xxxx|
xxxxxxx[control signal]
control signal: 0 output: data input1
control signal: 1 output: data input0
MULTIPLEXERS
-purpose
choosing between the CPU’s registers
DECODERS
-i/o
-n inputs
-2^n outputs (2^n combinations of n, ~n inputs)
input determines what gate is opened
we choose the gate instead of the input
the gate that gets all 1 is “activated”
DECODERS
-structure
in0—|————–>[GATE0]
[NOT gate]—–>[GATE1]
-AND gates when more than 1 inputs
in0: 0 activation: GATE1
in0: 1 activation: GATE0
DECODERS
-purpose
activate memory for read/write
lock/unlock memory
SHIFTER
-i/o
-n inputs
-1 control signal
-n outputs
SHIFTER
-structure
d0 ——–>and \
xxx|——–^ xxx --————>s0
xxx|—->|-and / \ _______
d1- | —- |xxxxxxxxx _______ or
xxx|xxx|-and \ /
xxx|xxx|—–^ ` -/————->s1
d2- | - | ->and /
xxx| not
xxx|—- |
xxxc
SHIFTER
-purpose
does binary shift
c=0 -> left shift
c=1 -> right shift
1-bit HALF-ADDER
adding bits can be done with XOR gate
must calculate carry if both bits are one
A——————>[XOR gate]———->sum
B——— | ————^
xxxxxxx|xxx|
xxxxx[AND gate]——->carry
1-bit FULL-ADDER
in full adder there must be a carry in as well as a carry out
xxxxxxxxxxxxxxxxxxxxxx carry in
xxxxxxxxxxxxxxxxxxxxxxxx|xxxxx|
A——————>[XOR gate]–|— –>[XOR gate]
B——— | ————^xxxxxxx|xx|
xxxxxxx|xxx|xxxxxxxxxxxx|xx|
xxxxxx[AND gate]——->[OR gate]——> carry out
N-bit FULL-ADDER
N-bit adder is multiple full adders connected
carryin==0 —>[1bit ADDER]—->[1bit ADDER] . . . —>carryout
ALU
ALU is complex in structure
it does:
-AND
-OR
-NOT
-ADD
uses decoder to enable the operation
like the adders there is 1bit alu and it is connected serially to make n-bit
NOR SR LATCH
s——-nor-|——q’
xxxxxx \ |
xxxxxxx \/
xxxxxxx /\
xxxxxxx/ \
xxxxxx/ |
r——-nor–|—-q
!! nor gate: if at least one input is 1 output is 0
it is a loop with stable states
s=set
r=reset
case1: s==0 r==1->q=0
–>r=0 state doesnt change (memory)
case2: s==1 r==0 ->q=1
–> s=0 state doesnt change
s=0 r=0 –> memory state
!!case3: s==1 r==1 invalid gives q=q’
when we change to state r=0 s=0 we get non
determinable result yields 2 conditions
purpose: memory
CLOCKED NOR SR LATCH
s—–and——-nor-|——q’
xxxxxx|xxxxx \ |
xxxxxx|xxxxxx \/
clock-|xxxxxxx/\
xxxxxx|xxxxx / \
xxxxxx| xxxx/ |
r—–and——-nor–|—-q
same as sr latch but when clock ==0 we cannot make changes
