CPU Design Items Flashcards
What is logic gate
In MIPS, logic gates like AND, OR, and XOR are implemented using bitwise instructions (and, or, xor, nor) that directly manipulate individual bits in registers, enabling efficient hardware-level logical operations.
What is a register?
32 bits
Register File
a collection of registers in which any register can be read or written by specifying the number of the register in the file.
Input:To write a data word, we will need two inputs: one to specify the register number to be written and one to supply the data to be written into the register.
Output:the contents of whatever register numbers are on the Read register inputs.
File consists of 32 general purpose resisters each 32 bits.
Multuplexor
selects from among several inputs based on the setting of its control lines. The control lines are set based primarily on information taken from the instruction being executed.
What is an adder?
increments the PC to the address of the next instruction
To execute any instruction we start by fetching it from memory. To prepare for the next instruction, we must also increment the program counter so that it points at the next instruction, 4 bytes later.
What is an ALU? What inputs and outputs does a MIPS ALU have?
hardware that performs addition, subtraction, and usually logical operations such as AND and OR
Input A: Contents of $t1.
Input B: Contents of $t2.
ALU Control Signal: 0010 (Add operation).
Outputs:
Result: The sum of $t1 and $t2, written to $t0.
Zero Flag: 0 (non-zero result).`
What is datapath?
A datapath is the hardware subsystem within a processor responsible for carrying out all the computational operations. It connects and coordinates the flow of data between various components,
What is Control circuitry?
has the instruction as an input, used to determine how to set the control lines for the functional units and two of the multiplexors.
Single Cycle
In a single-cycle CPU, every instruction is executed in a single clock cycle. This means that all operations—fetching the instruction, decoding it, executing the operation, accessing memory, and writing back results—must be completed within one clock cycle.
Multi Cycle CPU
multi-cycle CPU, instructions are divided into multiple stages, and each stage is completed in one clock cycle. The processor reuses functional units (e.g., ALU, memory) across different stages, and each instruction may take several clock cycles to execute
Pipelining
Pipelining in a CPU is a technique where multiple instructions are overlapped during execution by dividing the instruction execution process into discrete stages. Each stage is handled by a dedicated hardware unit, and different stages of different instructions are executed simultaneously. the total execution time for multiple instructions is reduced.
data hazard
If an instruction needs data that is not yet available because a previous instruction has not completed, the pipeline might stall.
Data Forwarding
Data Forwarding (or bypassing) is a hardware technique used to resolve RAW hazards by passing the data directly from one pipeline stage to another without waiting for the instruction to complete. Only works sometimes
add $t0, $t1, $t2 # EX stage calculates $t0
sub $t3, $t0, $t4 # EX stage cannot proceed until $t0 is written. Would not work for lw.
Control Hazard
A control hazard occurs in a pipelined CPU when the processor encounters a branch instruction (e.g., beq, bne) and does not know which instruction to fetch next. This happens because the decision to branch depends on the outcome of a comparison,
Control Hazard occurs
beq $t0, $t1, label # Should we branch to “label” or continue sequentially?
