CPU Flashcards
What registers are involved in Von Neumann architecture?
Memory Address Register
Memory Data Register
Program Counter
Accumulator
Current Instruction Register
What does the Program Counter do?
Stores the location of the next instruction to execute
What does the Memory Address Register do?
Stores the address of a location in memory that is currently being read from or written to
What does the Memory Data Register do?
Holds the data that has just been retrieved from memory or the data that is about to be written to memory
What does the Accumulator do?
Stores to results of calculations from the Arithmetic Logic Unit (ALU)
What does the Current Instruction Register do?
Stores the current instruction being executed in the CPU
What other components are part of the Von Neumann architecture?
Decode Unit,
Control Unit,
Arithmetic Logic Unit,
Busses,
Cache
What are the 3 Busses in Von Neumann architecture?
Address Bus,
Data Bus,
Control Bus
What does the Decode Unit do?
Decodes the current instruction to be executed
What does the Control Unit do?
Controls the flow of data in the CPU by telling each component what to do and when to do it e.g. telling memory to read at this exact moment
What does the Arithmetic Logic Unit do?
Performs arithmetic operations and logical operations on data, allowing the CPU to perform many calculations
What does the Cache do?
Stores frequently used instructions and data close to the CPU for much faster access compared to RAM, because it is so much closer to the proccessing unit
What are the 3 factors that determin CPU performace?
Cache Size,
Clock Speed,
Number of Cores
How does Cache Size affect CPU performace?
Larger cache size increases CPU performance by allowing for more frequently used instructions and data to be held much closer to the CPU for much faster access
How does Clock Speed affect CPU performance?
A higher clock speed increases the number of fetches the CPU can make per second increasing performance as more instructions can be completed faster as more a fetched
How does Number of Cores affect CPU performance?
A larger number of cores can increase performance by allowing the CPU to proccess multiple threads at the same time, but is not just a simple increase as the more cores there are the more time they have to spend communicating and coordinating with each other
Describe the entire Fetch-Decode-Execute Cycle
Fetch - Program Counter gives its location data to the Memory Address Register. The Program Counter then increments by 1. The Memory Address Register sends the address it has along the address bus to memory to read the instruction at that location. The Control Unit tells the memory to read now and the data is put on the data bus to be moved into the Memory Data Register. From there the instruction is moved into the Current Instruction Register to be decoded and executed.
Decode - The instruction is decoded by the Decode Unit, to know exactly what to do next
Execute - The Control Unit uses the decoded instruction and executes the instruction e.g. reading a value from memory into the accumulator
What is an instruction set?
A list of machine code instructions a specific CPU can recognise
What are some other factors that affect CPU performance?
Width and speed of the Data bus
Size of registers
How does width on the data bus affect CPU performance?
larger width increases performance as more data and instructions can be given to the CPU at once
How does speed on the data bus affect CPU performance?
Data fetched from memory reaches the CPU much faster, with higher data bus speeds, causing the CPU to stall for less time waiting for data and instructions increasing CPU performance
How does register size affect CPU performace?
Larger register sizes can allow the CPU to hold more data and interact with more memory as addresses stored can be larger, this allows the CPU to accept more data at once as well to be worked on, increasing performance
What is Pipelining?
While one instruction is being executed another one can be being decoded and another being fetched, rather than waiting for one instruction to be fully executed then fetching, decoding and executing the next one, making the CPU much faster
What is a problem caused by a branch for pipelining?
When a branch occurs the Pipeline may have to be flushed as the next instructions that are in the pipeline aren’t supposed to be executed, however they are still put into the pipeline as if its a conditional branch the branch may not occur and the CPU can keep going without having to flush the pipeline
What are the different types of CPU architecture?
Von Neumann
Havard
Contemporary
What is the difference between a Von Neumann and Havard CPU?
Havard CPUs store instructions and data in seperate peices of memory hardware, allowing for Havard CPUs to be fetching data and instructions at the same time, as well as being very hard to control as instructions cannot be overridden by a program.
Von Neumann stores instructions and data in the same memory hardware, and it only has one bus for data and instructions meaning it has to wait for a piece of data or an instruction to be fetched before being able to fetch something else
What are some features of Contemporary architectures?
SIMD - Single Instruction Multiple Data
MIMD - Multiple Instruction Multiple Data
What does SIMD do?
Performs one instruction on many pieces of data, this can be split across several cores (like a GPU) to perform this instruction much faster
What does MIMD do?
Performs multiple instructions on multiple pieces of data, allowing for the instructions to be easily split across several cores to perform the instructions faster
What is a RISC?
Reduced Instruction Set Computer
A computer with a small number of simple instructions
What is a CISC?
Complex Instruction Set Computer
A computer with a large number of complex instruction that may take several clock cycles to do and that requires specific hardware to do these instructions
What are some characteristics of RISC?
Uses less power than CISC due to less transistors for speific hardware
Easier to cool as there are less transistors turning on and off
Only one cycle per instruction
Smaller number of addressing modes
Every instruction has the same format
Large number of instructions are needed to perform tasks
What are some characteristics of CISC?
Uses more power due to more specific hardware
Harder to cool as more transistors turn on and off due to specific hardwre
Multiple cycles can be taken for each instruction
Instruction formats can be different for each instruction
Smaller number of instructions need to be executed to perform tasks
Larger number of addressing modes
What is a Co-Proccessor?
A piece of extra hardware that takes away difficult jobs from the CPU
What are some examples of Co-Proccesors?
GPU (Graphics Processing Unit)
NIC (Network Interface Card),
Audio Card,
Memory Management,
Hardware Firewall,
Cryptographic Hardware
What are the names we give to mutli-core CPUs?
Single Core
Dual Core
Quad Core
Hexacore (6 cores)
Octacore (8 cores)
16-Core
32-Core
64-Core
What are the different levels of Cache in a CPU?
Level 1 - on each individual core
Level 2 - accessible by every core close to all the cores
Level 3 - furthest away accessible by every core as well
What is a thread?
A seperate flow of control, each thread having its own program counter so that they can be running different code
When can and can’t threads be used?
Count to 100 can’t be threaded as 20 must follow 19
Calculating 10! can be threaded as you can multiply in any order and the result is the same
How would threading be used in a software that queries a remote database?
Thread 1 = User Interface
Thread 2 = Networking
Thread 3 = Business Logic
What is parallel processing?
Running several threads at the same time by running them across several cores
