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OOP > Computing Systems W8 part 1 > Flashcards

Computing Systems W8 part 1 Flashcards

1
Q

What is Operating System?

A

A program that acts as an intermediary between a user of a computer and the computer hardware

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2
Q

OS goals (3)

A
  • Execute user programs and make solving user problems easier
  • Make the computer system convenient to use
  • Use the computer hardware in an efficient manner
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3
Q

What are the components of a computer system (4) ?

A

Hardware
OS
Application programs
Users

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4
Q

hardware

A

provides basic computing resources

ex. CPU, Memory, I/O devices

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5
Q

Operating System

A

controls and coordinates use of hardware

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6
Q

Application programs

A

define the ways in which the system resources are used to solve the computing problems of the users

ex. word processors, compilers, web browsers, database systems, video games

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7
Q

users

A

ex. people, machines, other computers

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8
Q

OS main jobs

A
  • Resource allocations: manages all resources and decides between conflicting requests for efficient and fair resource use
  • Control program to prevent errors and improper use of the computer
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9
Q

bootstrap

A

the first program to run on computer power-on. loads OS into RAM to start up computer.

Stored in ROM/EPROM ( within firmware) and initializes all aspects of the system. Loads
the operating system

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10
Q

ROM/EEPROM

A

read only memory (non-volatile)
electronically erasable programmable read-only memory

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11
Q

device controller (4)

A

The device controller manages the hardware-specific details of the I/O device
-managing device registers,
-generate & send interrupts to CPU
-maintains local buffer storage
-can connect to multiple I/O devices

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12
Q

device driver

A

acts as an interface between the device controller and the operating system
provides a standardized interface for the OS to communicate with different types of devices, abstracting the hardware details.

ex. translates high-level commands and requests from the OS into low-level commands that the device controller understands

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13
Q

single processor systems (single processing core)

A

computer system with one CPU with a single processing core
-general purpose core
-special purpose core

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14
Q

core

A

component of CPU that executes instructions and registers for storing data locally
- ALU
- Control Unit
- Registers
- Cache

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15
Q

multiprocessor system

A

system with multiple CPUs
-CPU can have one or multiple cores

processors share computer bus and sometimes clock, memory, and peripheral devices

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16
Q

multiprocessor system advantages

A

increased throughput*
(more work, less time)

Economy of scale (lower cost with higher processing power)

Increased reliability (graceful degradation/fault tolerance)

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17
Q

multiprocessor system disadvantages

A

overhead incurred keeping all parts working correctly

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18
Q

symmetric multiprocessing architecture (SMP)

A

Multiple processors with its own CPU, set of registers, and local cache that share main memory over the system bus

each peer CPU performs all tasks including OS functions and user processes

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19
Q

SMP advantages

A
  • N processes can run if there are N CPUs without performance deterioration
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20
Q

SMP disadvantages

A
  • Separate CPUs may lead to one to sit idle while the other is overloaded leading to inefficiencies
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21
Q

multicore systems

A

multiple computing cores on a single ship

  • more efficient than multichip systems with single cores (on-chip communication is faster than between-chip communication) & uses less power
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22
Q

Computer-system organization

A

One or more CPUs, device controllers connect through common bus providing access to shared memory. Concurrent execution of CPUs and devices compete from memory cycles

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23
Q

local buffer

A

Local storage within each device controller

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24
Q

I/O transfer

A

CPU moves data from / to main memory to / from local buffers

I/O moves data from the device to local buffer within the device controller.

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25
Q

Interrupt pathway

A

User or software-generated interrupt is triggered

interrupt transfers control to ISR (Interrupt service routine) via interrupt vector

Address of interrupt instruction is then saved

CPU is then stopped to process interrupt (transfers execution to address of interrupt instructions)

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26
Q

Interrupt vector

A

Contains all the address of all the service routines

27
Q

Interrupt: I/O to/from CPU transfer

A

device controller raises an interrupt by asserting a signal on the
interrupt request line

CPU catches the interrupt and dispatches it to the
interrupt handler

the handler clears the interrupt by servicing the device.

28
Q

Direct memory access (DMA) structure

A

used for high-speed I/O devices

Device controller transfers blocks of data from device local storage directly to main memory via system bus (without CPU)

Only one interrupt is created for every block (instead of one interrupt per byte)

29
Q

Wait instruction

A

CPU needs to pause and wait for the next interrupt. This instruction essentially puts the CPU in an idle state until an interrupt occurs.

30
Q

wait loop

A

CPU repeatedly checks for the occurrence of a particular condition, often using a “polling” mechanism. This can create contention for memory access, as the CPU is frequently accessing memory to check for the condition.

31
Q

system call

A

mechanism by which a program requests a service from the operating system

ex. request the OS to allow the user program to wait for the completion of an I/O operation

32
Q

device status table

A

Allows the OS to keep track of the status of various devices and manage their operations effectively

It contains entries for each I/O device connected to the system, providing information such as the type of the device, its address, and its current state.

33
Q

OS device status table management

A

OS indexes device table for specific entry to determine current state and make any modifications to device state change

OS can insert interrupt into table entry to notify CPU to asynchronously interrupt the normal execution of the CPU and transfer control to a specific interrupt handler routine.

34
Q

RAM

A

random access memory

main memory that is volatile (will not save once power is off

35
Q

secondary storage

A

hard disks: inexpensive, trustworthy (time), and longevity in its use. But is slow, susceptible to creating heat/noise and can be damaged

solid-state disks: slightly faster than HDD, consume less power, and are smaller. But is more expensive, higher risk for poor data recovery, and limited capacity

36
Q

Storage system hierarchy comparator

A

speed
cost
volatility

37
Q

caching

A

copying information into faster storage system for more efficient read/write operations

ex. main memory is a cache for secondary storage

38
Q

Storage system hierachy

A

registers
cache
main memory
solid-state-disk
hard disk
optical disk
magnetic tape

39
Q

memory hierarchy

A

L0: Registers
L1: L1 cache (SRAM)
L2: L2 cache (SRAM)
L3: Main Memory (DRAM)
L4: Local secondary storage (local disks)
L5: Remote secondary storage (tapes, distributed files systems, web servers)

40
Q

cache example

A

search engines (google): search results are cached for frequently searched terms. Cache results can be quickly retrieved and improve the overall search experience

41
Q

graceful degradation

A

In the event of a failure or malfunction in one processor, the remaining processors can continue to execute tasks.

System still operates at reduced capacity rather than shutting down

42
Q

fault tolerance

A

Redundant components and error-checking mechanisms help in identifying and recovering from faults, ensuring continuous operation even in the presence of hardware or software failures.

(Redundancy means having duplicate or backup components that can take over in case of a failure.)

43
Q

Hot standby

A

In a multiprocessor system, if one processor fails, another standby processor can take over, ensuring continuous operation.

44
Q

Types of Multiprocessors

A

Asymmetric
Symmetric

45
Q

Asymmetric Multiprocessor (AMP) pros (3) & cons (2)

A

Pros
-Task-oriented
-efficient for specialized processing
-scalable

Cons
-can lead to resource underutilization
-complex task management.

46
Q

Symmetric Multiprocessor (SMP) pros (3) & cons (3)

A

Pros
-Task flexibility
-resource sharing
-ease of programming

Cons
-can have complexities in synchronization
-limited scalability
-potentially higher costs.

47
Q

Asymmetric Multiprocessor (AMP)

A

Processors have specific, dedicated tasks. Specialized for certain workloads. Tasks are not necessarily interchangeable between processors.

48
Q

Symmetric Multiprocessor (SMP)

A

All processors are identical and can perform any task. Workload is dynamically distributed among processors. Tasks are interchangeable between processors.

49
Q

Dual-core design

A

One physical chip (system) that contains two separate processing cores (CPUs)

Each core is capable of executing its own set of instructions independently. This allows the processor to handle multiple tasks simultaneously, improving overall performance and responsiveness.

50
Q

Storage-area network (SAN)

A

shared storage used by clustered system

51
Q

Clustered System

A

multiple independent computers (nodes or systems) are connected together to work as a single system.

These nodes communicate with each other over a network and may have their own processors, memory, and storage.

Each node in the cluster is a separate system, and they collaborate to solve a common problem or perform a task.

52
Q

Clustered System pros

A

Achieve high availability
(ability of a system to remain operational and accessible for a high percentage of time)

53
Q

Asymmetric clustering

A

one machine is on hot standby

simpler in design & focus is on having a backup system available

54
Q

Symmetric clustering

A

multiple nodes run application while monitoring each other

If a failure is detected in one node, the workload is redistributed among the remaining healthy nodes

better scalability and fault tolerance

55
Q

multiprogramming (batch system)

A

maximize CPU utilization and enhance overall system efficiency by allowing the CPU to switch between different programs.

56
Q

timeshare (multitasking)

A

CPU switches jobs so
frequently that users can interact with each job while it is running

response time < 1 second

57
Q

Dual-mode operation

A

CPU can operate on two different modes (user & kernel)

provides a level of protection and control over system resources.

58
Q

Kernel mode bit

A

0

A task will be executed on behalf of the OS

provides unrestricted access to hardware and system resources. Allows execution of privileged instructions and critical system tasks

59
Q

User mode bit

A

1

A task will be executed on behalf of the user

restricted access to system resources and functionalities. It can execute a set of instructions and application programs

60
Q

Kernel mode names

A

supervisor mode
system mode
privileged mode

61
Q

life cycle of instruction execution

A

(0): Kernel mode: bootstrap program
(1): User mode: user application
Interrupt/trap/system call switches to (0) kernel mode
(0): Kernel mode: execution of privileged instruction completes then switches back to user mode (1)
(1): User mode: user application is resumed

62
Q

trap

A

mechanism used to switch the CPU from user mode to kernel mode in response to a specific event

ex. user program executes and needs to perform privileged instruction. It makes a system call that generates a trap causing CPU to switch to kernel mode (0)

63
Q

Timer (dual-mode)

A

Prevents user application from infinite loops and hogging resources

Once user process begins a timer starts counting down to generate an interrupt when time runs out which transfers control back to OS

64
Q

Multi-mode operations (virtual machine manager VMM)

A

extension of dual-mode operation that have additional modes beyond user and kernel

ex. VMM mode supports a mode for virtualization. When virtual machine runs on a host system the CPU can operate on a mode that allows CMM to manage execution of multiple VMs

OOP (5 decks)

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