Computing Systems Final

Question 1

valid

Answer 1

Cache component that is set when the cache entry is being used

Question 2

Tag

Answer 2

The memory address mapped to the entry

Question 3

Hit ratio (h)

Answer 3

Percentage of accesses that hit the cache

Question 4

Miss ratio (1 – h)

Answer 4

Percentage of access that miss the cache

Question 5

Cache access time (c)

Answer 5

Time to access the cache (Both hit and miss)

Question 6

Main memory access time (m)

Answer 6

Time to access main memory

Question 7

Average memory latency

Answer 7

c + (1 – h) * m

Question 8

How do you improve the average memory latency?

Answer 8

Increase hit rate
Decrease cache access time
Decrease memory access time

Question 9

Principle of Spatial Locality

Answer 9

If we reference a memory location (e.g., 1000),
we are more likely to reference a location near it (e.g., 1001) than some random location

Question 10

Examples of spatial locality in programs?

Answer 10

• Arrays
• Instructions (PC + 1)

Question 11

cache blocks

Answer 11

store multiple words in a single cache line

Question 12

write through

Answer 12

Store instructions write to both memory and the cache

Question 13

Write policy disadvantage

Answer 13

cache and memory inconsistent

Question 13

Write policy advantage

Answer 13

fewer stores to memory

Question 14

write back

Answer 14

Only write the contents back to memory once cache block is evicted

Question 14

write allocate advantage

Answer 14

it exploits spatial and temporal
locality

Question 14

dirty bit

Answer 14

set to 1 anytime a store instruction modified memory

Question 14

Write allocate

Answer 14

Stores that miss the cache are brought into the cache

Question 15

write no-allocate

Answer 15

Stores that miss the cache will not be brought into the
cache

Question 16

content addressable memory

Answer 16

Search for an element by content instead of by address

ex. Cache

Question 17

Fully associative

Answer 17

Any memory location can be stored in any block (cache line)

Question 18

Fully associative disadvantages

Answer 18

Must check every tag in the cache

Question 19

Direct Mapped

Answer 19

A memory location can only reside in one particular block.

Data from memory address is mapped to cache
block using a modular approach

Question 20

Direct mapped advantages

Answer 20

Only need to check one tag. improves cache access time

Question 21

N-way set associative

Answer 21

A memory location can only reside in a particular set of
N blocks

Question 22

Direct mapped example

Answer 22

data from memory address 11 maps to cache block 3, since 11 mod 4 = 3

Question 23

Direct Mapped Disadvantage

Answer 23

Several block addresses can compete for a cache line while other cache
lines are unused