Computer Organization and Architecture Flashcards

1
Q

What is the file format of a file with the signature “{\rtf”

A

.rtf (Rich Text Format)

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2
Q

What is the file format of a file with the signature “ID3”

A

.mp3 (MPEG Audio Layer-3)

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3
Q

What is the file format of a file with the signature “RIFF”

A

.wav (Wave)

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4
Q

What is the file format of a file with the signature “BM”

A

.bmp (Bitmap Image)

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5
Q

What is the file format of a file with the signature “……JFIF”

A

.jpeg (Joint Photographic Experts Group)

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6
Q

What is the file format of a file with the signature “ID3”

A

.mpeg (Moving Picture Experts Group)
AND
.mp3 (MPEG Audio Layer-3)

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7
Q

What is the file format of a file with the signature “MZ”

A

.exe (Executable File Format)

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8
Q

What is the file format of a file with the signature “.ELF”

A

.elf (Executable and Linkable Format)

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9
Q

What is the file format of a file with the signature “…”

A

.gz (GZIP)

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10
Q

What is the file format of a file with the signature “PK”

A

.zip (ZIP)

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11
Q

What are file format signatures written in?

A

Hexadecimal

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12
Q

What is the Prefix and Symbol for Quintillion?

A

Exa (E)

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13
Q

What is the Prefix and Symbol for Quadrillion?

A

Peta (P)

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14
Q

What is the Prefix and Symbol for Trillion?

A

Tera (T)

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15
Q

What is the Prefix and Symbol for Billion?

A

Giga (G)

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16
Q

What is the Prefix and Symbol for Million?

A

Mega (M)

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17
Q

What is the Prefix and Symbol for Thousand?

A

Kilo (K)

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18
Q

What is the Prefix and Symbol for Thousandth?

A

milli (m)

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19
Q

What is the Prefix and Symbol for Millionth?

A

micro (μ)

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20
Q

What is the Prefix and Symbol for Billionth?

A

nano (n)

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21
Q

What is the Prefix and Symbol for Trillionth?

A

pico (p)

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22
Q

What is the Prefix and Symbol for Quadrillionth?

A

femto (f)

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23
Q

What is the Prefix and Symbol for Quintillionth?

A

atto (a)

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24
Q

Time and frequency have a base of 10 and the exponent increases by intervals of ___?

A

3

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25
Q

Data Storage has a base of 2 and the exponent increases by intervals of __?

A

10

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26
Q

For the LMC what is the 1 Digit Opcode and 2 Digit Operand for Halt (HLT)?

A

000

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27
Q

For the LMC what is the 1 Digit Opcode and 2 Digit Operand for ADD?

A

1XX

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28
Q

For the LMC what is the 1 Digit Opcode and 2 Digit Operand for SUBTRACT? (SUB)

A

2XX

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29
Q

For the LMC what is the 1 Digit Opcode and 2 Digit Operand for STORE? (STA)

A

3XX

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30
Q

For the LMC what is the 1 Digit Opcode and 2 Digit Operand for LOAD? (LDA)

A

5XX

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31
Q

For the LMC what is the 1 Digit Opcode and 2 Digit Operand for BRANCH UNCONDITIONAL? (BRA)

A

6XX

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32
Q

For the LMC what is the 1 Digit Opcode and 2 Digit Operand for BRANCH ON ZERO? (BRZ)

A

7XX

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33
Q

For the LMC what is the 1 Digit Opcode and 2 Digit Operand for BRANCH ON POSITIVE? (BRP)

A

8XX

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34
Q

For the LMC what is the 1 Digit Opcode and 2 Digit Operand for INPUT? (INP)

A

901

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35
Q

For the LMC what is the 1 Digit Opcode and 2 Digit Operand for OUTPUT? (OUT)

A

902

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36
Q

For the LMC what is the 1 Digit Opcode and 2 Digit Operand for DATA?

A

there isn’t one

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37
Q

What F-D-E Instruction is being described here and what is the code?

PC -> MAR
MDR -> IR

A

000, HLT

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38
Q

What F-D-E Instruction is being described here and what is the code?

PC -> MAR
MDR -> IR
IR[ADDR] -> MAR
A + MDR -> A
PC + 1 -> PC
A

1XX, ADD

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39
Q

What F-D-E Instruction is being described here and what is the code?

PC -> MAR
MDR -> IR
IR[ADDR] -> MAR
A - MDR -> A
PC + 1 -> PC
A

2XX, SUB

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40
Q

What F-D-E Instruction is being described here and what is the code?

PC -> MAR
MDR -> IR
IR[ADDR] -> MAR
A  -> MDR
PC + 1 -> PC
A

3XX, STA

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41
Q

What F-D-E Instruction is being described here and what is the code?

PC -> MAR
MDR -> IR
IR[ADDR] -> MAR
MDR -> A
PC + 1 -> PC
A

5XX, LDA

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42
Q

What F-D-E Instruction is being described here and what is the code?

PC -> MAR
MDR -> IR
IR[ADDR] -> PC

A

6XX, BRA

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43
Q

What F-D-E Instruction is being described here and what is the code?

PC -> MAR
MDR -> IR
IF A == 0 THEN
    IR[ADDR] -> PC
ELSE
    PC + 1 -> PC
A

7XX, BRZ

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44
Q

What F-D-E Instruction is being described here and what is the code?

PC -> MAR
MDR -> IR
IF A >= 0 THEN
    IR[ADDR] -> PC
ELSE
    PC + 1 -> PC
A

8XX, BRP

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45
Q

What F-D-E Instruction is being described here and what is the code?

PC -> MAR
MDR -> IR
INBOX -> A
PC + 1 -> PC

A

901, INP

46
Q

What F-D-E Instruction is being described here and what is the code?

PC -> MAR
MDR -> IR
A -> OUTBOX
PC + 1 -> PC

A

902, OUT

47
Q

The architecture concept that underlies the Von Neumann and Harvard architectures

A

Stored-Program Concept

48
Q

A register that can be directly accessed by the programmer for any purpose

A

General-Purpose Register

49
Q

An expression composed of Boolean variables and logical connectives

A

Boolean Expression

50
Q

The numeric value that represents an instruction to the CPU

A

Opcode

51
Q

The part of the CPU that manages data passed to or fetched from memory

A

Memory Management Unit (MMU)

52
Q

The vocabulary of commands understood by the CPU

A

Instruction set architecture

53
Q

The part of the CPU that performs the fetch and decode steps of an assembly instruction

A

Control Unit (CU)

54
Q

The part of the CPU that performs arithmetic and logic operations

A

Arithmetic Logic Unit (ALU)

55
Q

The process used by the CPU to retrieve, interpret, and perform each instruction of a program

A

Fetch-Decode-Execute (F-D-E)

56
Q

ARM _______ dictate which instructions and architectural features are available to a process.

A

modes of operation

57
Q

Which ARM privilege level allows the FEWEST number of features of the architecture to be available to a process?

A

PL0

58
Q

ARM uses _____ to move data from register-to-register, register-to-memory, and memory-to-register.

A

data movement instructions

59
Q

The _____ is a last-in-first-out memory structure used by ARM for short term storage of information by the CPU.

A

stack

60
Q

A _____ in ARM, is a block of code labeled for reuse.

A

subroutine

61
Q

ARM _____ instructions perform logical operations on 0s and 1s.

A

Boolean Logic

62
Q

What are the ARM Modes of Operation?

A

User (usr) - User mode is the default ARM program execution state and is used for executing most application programs

System (sys) - Runs privileged OS tasks (routine OS business)

FIQ - Used when handling high priority (fast) interrupts

IRQ - Used when handling low priority (normal) interrupts

Supervisor (svc) - Protected mode for the OS (system calls)

Abort - Used to handle memory access violations

Undef - Used to handle undefined or unimplemented instructions

Secure Monitor (mon) - Used to transfer control from non-secure to secure and vice versa by the processor.

63
Q

ARM _____ instructions operate on integers and floating-point numbers.

A

Arithmetic

64
Q

ARM _____ are hardware enforced permissions to ensure system security through process isolation.

A

Privilege levels

65
Q

In ARM, _____ defines where to find the data (operand) to be manipulated by the instruction (opcode).

A

Operand Addressing Mode

66
Q

ARM _____ instructions use branching to change the order in which the program executes.

A

flow control

67
Q

What are the ARM control and status registers?

A
Program Counter (control)
CPSR (Current Program Status Register) (status)
68
Q

The _____ registers hold information about the most recently performed ALU operation, memory alignment, endianess, enabling and disabling of interrupts, and set processor-operating mode.

A

control and status

69
Q

The _____ register points to the next instruction in memory.

A

Program Counter (PC)

70
Q

The _____ stores the return address for subroutines.

A

Link Register (LR)

71
Q

_____ registers can be directly accessed by the programmer for any purpose.

A

General-Purpose

72
Q

_____ registers are used for base locations for program instructions, data, and the stack.

A

Segment

73
Q

The _____ points to the top of the stack.

A

Stack Pointer (SP)

74
Q

The _____ holds the current condition of the program.

A

Current Program Status Register (CPSR)

75
Q

The Operand Addressing mode of the following instruction is:

ldr r0, [r1], #24

A

Post-Indexed Memory

76
Q

The Operand Addressing mode of the following instruction is:

sub r0, r7, r6

A

Register

77
Q

The Processor Architecture and Operand Addressing mode of the following instruction is:

ldr r0, [pc, #8]

A

ARM/PC-Relative

78
Q

The Operand Addressing mode of the following instruction is:

ldr r0, [r1]

A

Register Indirect Memory

79
Q

The Processor Architecture and Operand Addressing mode of the following instruction is:

str r0, [r3]

A

ARM/Register Indirect Memory

80
Q

The Operand Addressing mode of the following instruction is:

str r0, [r1, #8]!

A

Pre-indexed memory

81
Q

The Operand Addressing mode of the following instruction is:

mov r0, #2

A

ARM/Immediate

82
Q

The Operand Addressing mode of the following instruction is:

add r0, #4, #6

A

Immediate

83
Q

Which registers are general-purpose registers in an ARM processor

A

r0-r12

84
Q

Which registers are segment registers in an ARM processor (the R number)

A

r13-r14

85
Q

What is another name for the ARM processor register R13?

A

Stack pointer (SP)

86
Q

What is another name for the ARM processor register R14?

A

Link Register (LR)

87
Q

Which register is the control register in an ARM processor

A

Program Counter (PC)

88
Q

Which register is the status register in an ARM processor

A

Current program status register (CPSR)

89
Q

Which ARM mode of operation is used to transfer between secure and non-secure?

A

Secure Monitor (mon)

90
Q

Which ARM mode of operation is used to handle undefined or unimplemented instructions?

A

Undef

91
Q

Which ARM mode of operation is used to handle memory access violations?

A

Abort

92
Q

Which ARM mode of operation is used to handle system calls?

A

Supervisor (svc)

93
Q

Which ARM mode of operation is used to handle low priority interrupts?

A

IRQ

94
Q

Which ARM mode of operation is used to handle high priority interrupts?

A

FIQ

95
Q

Which ARM mode of operation is used to handle privileged OS tasks?

A

System (sys)

96
Q

Which ARM mode of operation is used to handle routine user process execution?

A

User (usr)

97
Q

Which ARM privilege level is used while executing user processes?

A

PL0

98
Q

Which ARM privilege level is used while executing a system call?

A

PL1

99
Q

x86 _____ use branching to change the order in which the program executes.

A

Flow Control Instructions

100
Q

In x86 _____ defines where to find the data (operand) to be manipulated by the instruction (opcode).

A

Operand Addressing Mode

101
Q

x86 _____ work on integers and floating point numbers.

A

Arithmetic Instructions

102
Q

x86 uses _____ to move data from register-to-register, register-to-memory, and memory-to-register.

A

Data movement instructions

103
Q

in x86 the privilege levels are known as _____ and provide hardware enforced permissions to ensure system security much like ARM architecture.

A

Protection Rings

104
Q

x86 _____ perform logical operations on 0s and 1s.

A

Boolean Logic Instructions

105
Q

in x86, which category of registers do the following registers belong to?

AX, BX, CX, DX, SI, DI, BP, SP

A

General Purpose Registers (GPR)

106
Q

The _____ register is used for arithmetic and logical operations.

A

AX (Accumulator)

107
Q

The _____ points to the next instruction in memory.

A

IP (Instruction Pointer)

108
Q

Which category of registers do the following registers belong to?

IP, FLAGS

A

Control and Status registers

109
Q

Which category of registers do the following registers belong to?

CS, DS, SS, ES, FS, GS

A

Segment Registers

110
Q

The _____ register is used for string and loop operations.

A

CX (Counter)

111
Q

The _____ register holds the condition of the program.

A

FLAGS