Computer Organization and Architecture Flashcards
What is the file format of a file with the signature “{\rtf”
.rtf (Rich Text Format)
What is the file format of a file with the signature “ID3”
.mp3 (MPEG Audio Layer-3)
What is the file format of a file with the signature “RIFF”
.wav (Wave)
What is the file format of a file with the signature “BM”
.bmp (Bitmap Image)
What is the file format of a file with the signature “……JFIF”
.jpeg (Joint Photographic Experts Group)
What is the file format of a file with the signature “ID3”
.mpeg (Moving Picture Experts Group)
AND
.mp3 (MPEG Audio Layer-3)
What is the file format of a file with the signature “MZ”
.exe (Executable File Format)
What is the file format of a file with the signature “.ELF”
.elf (Executable and Linkable Format)
What is the file format of a file with the signature “…”
.gz (GZIP)
What is the file format of a file with the signature “PK”
.zip (ZIP)
What are file format signatures written in?
Hexadecimal
What is the Prefix and Symbol for Quintillion?
Exa (E)
What is the Prefix and Symbol for Quadrillion?
Peta (P)
What is the Prefix and Symbol for Trillion?
Tera (T)
What is the Prefix and Symbol for Billion?
Giga (G)
What is the Prefix and Symbol for Million?
Mega (M)
What is the Prefix and Symbol for Thousand?
Kilo (K)
What is the Prefix and Symbol for Thousandth?
milli (m)
What is the Prefix and Symbol for Millionth?
micro (μ)
What is the Prefix and Symbol for Billionth?
nano (n)
What is the Prefix and Symbol for Trillionth?
pico (p)
What is the Prefix and Symbol for Quadrillionth?
femto (f)
What is the Prefix and Symbol for Quintillionth?
atto (a)
Time and frequency have a base of 10 and the exponent increases by intervals of ___?
3
Data Storage has a base of 2 and the exponent increases by intervals of __?
10
For the LMC what is the 1 Digit Opcode and 2 Digit Operand for Halt (HLT)?
000
For the LMC what is the 1 Digit Opcode and 2 Digit Operand for ADD?
1XX
For the LMC what is the 1 Digit Opcode and 2 Digit Operand for SUBTRACT? (SUB)
2XX
For the LMC what is the 1 Digit Opcode and 2 Digit Operand for STORE? (STA)
3XX
For the LMC what is the 1 Digit Opcode and 2 Digit Operand for LOAD? (LDA)
5XX
For the LMC what is the 1 Digit Opcode and 2 Digit Operand for BRANCH UNCONDITIONAL? (BRA)
6XX
For the LMC what is the 1 Digit Opcode and 2 Digit Operand for BRANCH ON ZERO? (BRZ)
7XX
For the LMC what is the 1 Digit Opcode and 2 Digit Operand for BRANCH ON POSITIVE? (BRP)
8XX
For the LMC what is the 1 Digit Opcode and 2 Digit Operand for INPUT? (INP)
901
For the LMC what is the 1 Digit Opcode and 2 Digit Operand for OUTPUT? (OUT)
902
For the LMC what is the 1 Digit Opcode and 2 Digit Operand for DATA?
there isn’t one
What F-D-E Instruction is being described here and what is the code?
PC -> MAR
MDR -> IR
000, HLT
What F-D-E Instruction is being described here and what is the code?
PC -> MAR MDR -> IR IR[ADDR] -> MAR A + MDR -> A PC + 1 -> PC
1XX, ADD
What F-D-E Instruction is being described here and what is the code?
PC -> MAR MDR -> IR IR[ADDR] -> MAR A - MDR -> A PC + 1 -> PC
2XX, SUB
What F-D-E Instruction is being described here and what is the code?
PC -> MAR MDR -> IR IR[ADDR] -> MAR A -> MDR PC + 1 -> PC
3XX, STA
What F-D-E Instruction is being described here and what is the code?
PC -> MAR MDR -> IR IR[ADDR] -> MAR MDR -> A PC + 1 -> PC
5XX, LDA
What F-D-E Instruction is being described here and what is the code?
PC -> MAR
MDR -> IR
IR[ADDR] -> PC
6XX, BRA
What F-D-E Instruction is being described here and what is the code?
PC -> MAR
MDR -> IR
IF A == 0 THEN
IR[ADDR] -> PC
ELSE
PC + 1 -> PC
7XX, BRZ
What F-D-E Instruction is being described here and what is the code?
PC -> MAR
MDR -> IR
IF A >= 0 THEN
IR[ADDR] -> PC
ELSE
PC + 1 -> PC
8XX, BRP
What F-D-E Instruction is being described here and what is the code?
PC -> MAR
MDR -> IR
INBOX -> A
PC + 1 -> PC
901, INP
What F-D-E Instruction is being described here and what is the code?
PC -> MAR
MDR -> IR
A -> OUTBOX
PC + 1 -> PC
902, OUT
The architecture concept that underlies the Von Neumann and Harvard architectures
Stored-Program Concept
A register that can be directly accessed by the programmer for any purpose
General-Purpose Register
An expression composed of Boolean variables and logical connectives
Boolean Expression
The numeric value that represents an instruction to the CPU
Opcode
The part of the CPU that manages data passed to or fetched from memory
Memory Management Unit (MMU)
The vocabulary of commands understood by the CPU
Instruction set architecture
The part of the CPU that performs the fetch and decode steps of an assembly instruction
Control Unit (CU)
The part of the CPU that performs arithmetic and logic operations
Arithmetic Logic Unit (ALU)
The process used by the CPU to retrieve, interpret, and perform each instruction of a program
Fetch-Decode-Execute (F-D-E)
ARM _______ dictate which instructions and architectural features are available to a process.
modes of operation
Which ARM privilege level allows the FEWEST number of features of the architecture to be available to a process?
PL0
ARM uses _____ to move data from register-to-register, register-to-memory, and memory-to-register.
data movement instructions
The _____ is a last-in-first-out memory structure used by ARM for short term storage of information by the CPU.
stack
A _____ in ARM, is a block of code labeled for reuse.
subroutine
ARM _____ instructions perform logical operations on 0s and 1s.
Boolean Logic
What are the ARM Modes of Operation?
User (usr) - User mode is the default ARM program execution state and is used for executing most application programs
System (sys) - Runs privileged OS tasks (routine OS business)
FIQ - Used when handling high priority (fast) interrupts
IRQ - Used when handling low priority (normal) interrupts
Supervisor (svc) - Protected mode for the OS (system calls)
Abort - Used to handle memory access violations
Undef - Used to handle undefined or unimplemented instructions
Secure Monitor (mon) - Used to transfer control from non-secure to secure and vice versa by the processor.
ARM _____ instructions operate on integers and floating-point numbers.
Arithmetic
ARM _____ are hardware enforced permissions to ensure system security through process isolation.
Privilege levels
In ARM, _____ defines where to find the data (operand) to be manipulated by the instruction (opcode).
Operand Addressing Mode
ARM _____ instructions use branching to change the order in which the program executes.
flow control
What are the ARM control and status registers?
Program Counter (control) CPSR (Current Program Status Register) (status)
The _____ registers hold information about the most recently performed ALU operation, memory alignment, endianess, enabling and disabling of interrupts, and set processor-operating mode.
control and status
The _____ register points to the next instruction in memory.
Program Counter (PC)
The _____ stores the return address for subroutines.
Link Register (LR)
_____ registers can be directly accessed by the programmer for any purpose.
General-Purpose
_____ registers are used for base locations for program instructions, data, and the stack.
Segment
The _____ points to the top of the stack.
Stack Pointer (SP)
The _____ holds the current condition of the program.
Current Program Status Register (CPSR)
The Operand Addressing mode of the following instruction is:
ldr r0, [r1], #24
Post-Indexed Memory
The Operand Addressing mode of the following instruction is:
sub r0, r7, r6
Register
The Processor Architecture and Operand Addressing mode of the following instruction is:
ldr r0, [pc, #8]
ARM/PC-Relative
The Operand Addressing mode of the following instruction is:
ldr r0, [r1]
Register Indirect Memory
The Processor Architecture and Operand Addressing mode of the following instruction is:
str r0, [r3]
ARM/Register Indirect Memory
The Operand Addressing mode of the following instruction is:
str r0, [r1, #8]!
Pre-indexed memory
The Operand Addressing mode of the following instruction is:
mov r0, #2
ARM/Immediate
The Operand Addressing mode of the following instruction is:
add r0, #4, #6
Immediate
Which registers are general-purpose registers in an ARM processor
r0-r12
Which registers are segment registers in an ARM processor (the R number)
r13-r14
What is another name for the ARM processor register R13?
Stack pointer (SP)
What is another name for the ARM processor register R14?
Link Register (LR)
Which register is the control register in an ARM processor
Program Counter (PC)
Which register is the status register in an ARM processor
Current program status register (CPSR)
Which ARM mode of operation is used to transfer between secure and non-secure?
Secure Monitor (mon)
Which ARM mode of operation is used to handle undefined or unimplemented instructions?
Undef
Which ARM mode of operation is used to handle memory access violations?
Abort
Which ARM mode of operation is used to handle system calls?
Supervisor (svc)
Which ARM mode of operation is used to handle low priority interrupts?
IRQ
Which ARM mode of operation is used to handle high priority interrupts?
FIQ
Which ARM mode of operation is used to handle privileged OS tasks?
System (sys)
Which ARM mode of operation is used to handle routine user process execution?
User (usr)
Which ARM privilege level is used while executing user processes?
PL0
Which ARM privilege level is used while executing a system call?
PL1
x86 _____ use branching to change the order in which the program executes.
Flow Control Instructions
In x86 _____ defines where to find the data (operand) to be manipulated by the instruction (opcode).
Operand Addressing Mode
x86 _____ work on integers and floating point numbers.
Arithmetic Instructions
x86 uses _____ to move data from register-to-register, register-to-memory, and memory-to-register.
Data movement instructions
in x86 the privilege levels are known as _____ and provide hardware enforced permissions to ensure system security much like ARM architecture.
Protection Rings
x86 _____ perform logical operations on 0s and 1s.
Boolean Logic Instructions
in x86, which category of registers do the following registers belong to?
AX, BX, CX, DX, SI, DI, BP, SP
General Purpose Registers (GPR)
The _____ register is used for arithmetic and logical operations.
AX (Accumulator)
The _____ points to the next instruction in memory.
IP (Instruction Pointer)
Which category of registers do the following registers belong to?
IP, FLAGS
Control and Status registers
Which category of registers do the following registers belong to?
CS, DS, SS, ES, FS, GS
Segment Registers
The _____ register is used for string and loop operations.
CX (Counter)
The _____ register holds the condition of the program.
FLAGS
